77 Massachusetts Ave, Room 38-476
Cambridge, MA 02139
Tel: +1 617 253 6038
cjt@mit.edu

Education

MIT, PhD in Computer Science and Engineering, 1983
MIT, Electrical Engineer, 1978
MIT, SM in Electrical Engineering and Computer Science, 1978
Wesleyan University, BA magna cum laude in Physics, 1973

Professional Experience

Massachusetts Institute of Technology, Cambridge, MA
   Senior Lecturer Emeritus, Dept. of EECS (7/18 - present)
   Senior Lecturer, Dept. of EECS (4/97 - 6/18)
   Undergraduate Officer, Dept. of EECS (7/09 - 6/11, 6/15 - 6/18)
   Co-Director, CSAIL (7/11 - 5/12)
   Associate Director, LCS/CSAIL (9/01 - 6/04, 7/09 - 6/11)
   Special Assistant to the Dean of Engineering (1/98 - 6/99)
   Research Scientist, Lab for Computer Science (9/95 - 4/97)


Research: educational technology for design-oriented courses, System-on-chip architectures for FPGAs, system architectures for delivering information services, new infrastructure for World-Wide Web, very high performance DSP architectures, processor implementations for embedded applications.

Teaching:
Introduction to EECS II: Digital Communication Systems (6.02)
Computation Structures (6.004)
Interactive Tutor Systems (6.099)
Introductory Digital Systems Lab (6.111)
Multicore Systems Lab (6.173)
Introduction to VLSI Design (6.371)


Administration: Research Director for the T-Party project, a $45MM, 10-year research collaboration with Quanta Computer, Inc. Formerly Associate Director and then Co-Director of the MIT Laboratory for Computer Science, a large, interdepartmental lab with ~800 faculty, students and staff and an annual research volume of ~$45MM.

Other: Chair of client committee for Stata Center project (713,000SF complex designed by Frank O. Gehry & Assoc.).

VDD, Inc., Newton, MA
   President (6/95 - 12/97)



VLSI engineering services for clients including Lucent Technologies, Analog Devices, Simplex Solutions, Radiata Inc. Projects include:

architecture of Video DSP incorporating 16 Sparc processors, very high bandwidth memory interface, and several special purpose processing units. VHDL modeling, full custom mask design (.35u CMOS).

Synthesizable VHDL Version 8 Sparc processor module.

transistor-level simulator using table-lookup models and fast solution techniques for very large (> 1MM fets) circuits.

TLW, Inc., Burlington, MA
   Co-founder, vice president (8/89 - 6/95)



Designed custom CMOS VLSI modules for clients including AT&T, Analog Devices, Philips Consumer Electronics, Thomson Consumer Electronics. Projects include:

a Version 8 Sparc processor module for embedded applications (full custom .5u CMOS, 67MHz @ 2.7V, 85K transistors, 4mm^2).

a reconfigurable FFE/DFE equalizer for cable and broadcast QAM transmissions incorporating 30 complex/120 real taps and an on-chip 32-bit Sparc core which performed the adaptation computations. (full custom .5u CMOS, 3V, filter taps @ 64MHz, ?K transistors, 100mm^2).

RISC core and YUV interpolator/RGB conveter for AT&T AVP MPEG decoder chip (full custom .9u CMOS)

Several cell-based ASICs that performed system-layer demultiplexing for MPEG 1.5 and MPEG 2 transport streams (LSI Logic 100K and 300K standard cells).

a very-lower power 8-channel decimating filter for portable medical electronics (full custom .9u CMOS, 50K transistors).

Architecture and board-level design for Symbolics' XL1200, NX400P and MacIvory III hardware products.

A variety of CAD tools including gate- and transistor-level simulators that can handle very large circuits, concurrent fault simulation, all-angle mask tools.

Responsible for finance, administration, benefits; shared responsibility for business development.

Agile Systems, Inc., Cambridge, MA (8/88 - 8/89)
   Co-founder (8/88 - 8/89)



Undertook design of parallel system architecture for NASA space station utilizing multiple Lisp processor chips; designed FLEXFIR, a reconfigurable 40MHz FIR filter/interpolator for HDTV video signal processing. Responsible for technical and business contributions to joint TRW/Agile proposal to NASA.

Symbolics, Inc., Cambridge, MA
   Technical Director (1/86 - 8/88)
   Consultant for V.P. Technology (3/83 - 1/86)
   Co-founder, Technical Director (1/82 - 3/83)



Shared responsibility for technical and product planning. During consulting period developed hardware accelerator and support software for logic-level IC simulation. After January 1986, was a principal investigator in Advanced Hardware Development group, reporting to V.P. Technology. Projects include leading group responsible for developing system architectures and prototypes for symbolic multiprocessors; system architecture and board-level design for products utilizing VLSI processor (includes high-speed bus supporting symmetric multiprocessing, architecture and design for low-end "add-in" card for MAC II and PC/AT); integration of simulation accelerator into existing CAD tools and continued evolution of simulation algorithms embodied in the company's integrated CAD system; architecture and design of Laser Graphics Printer product line.

Massachusetts Institute of Technology, Cambridge, MA
   Assistant Professor, Dept. of EECS (6/83 - 1/86)
   Research and Teaching Assistant (9/73 - 6/83)



Teaching: participated in the development and teaching of M.I.T.'s core computer science courses "Structure and Interpretation of Computer Languages" and "Computation Structures"; also senior-level course on "Computer System Engineering". Served as undergraduate advisor and VI-A faculty advisor to Digital Equipment Corp.

Research Programs (at the MIT Laboratory for Computer Science):

transistor-level simulation tools for VLSI design. Developed the original switch-level simulation algorithms, later extended to include timing estimation based on RC trees. Two of the simulators, ESIM and RSIM, have been widely distributed in both the academic and industrial communities.

processor-independent computer systems. Was a principal developer of the NuMachine which along with the Stanford University Node (SUN) was the prototype for the current generation of workstations. Included specification of the NuBus, later codified as the IEEE 1196 bus, which forms the basis for the Apple Macintosh II and later machines; this bus originated the concept of "plug-and-play" peripherals.

portable compilers. Using a template-based machine specification, developed a family of portable C compilers for the (then) newly available microprocessors. These compilers were widely distributed as the first C implementations for the x86 and 68K processors.

Awarded IBM Faculty Development Grant in 1984 and 1985.

Consulting: Developed initial implementation of Viewlogic's ViewSim simulator. Other clients have included GTE Laboratories, Harris, Digital Equipment, RSA Security, Simplex Solutions, Analog Devices, Lucent Technologies, Curl Corporation, Radiata Communications, R3Logic Inc.,

Professional societies: active in reviewing papers for professional journals, ICCAD program committee. Associate guest editor for October 1986 and 1987 Special Issues of IEEE Transactions on CAD of Circuits and Systems. Member of Executive Committee for ICCAD 87.

Patent 7373639, System and method supporting type checking of options, issued May 13, 2008.

Patent 7340720, System and method supporting mapping of option bindings, issued March 4, 2008.

Patent 6769001, System and method supporting nonlocal values, issued July 27, 2004.

Patent 5034907, Dynamically Configurable Signal Processor and Processor Arrangement, issued July 23, 1991.

• C. J. Terman, "Simulation Tools for VLSI," in VLSI CAD Tools and Applications (W. Fichtner and M. Morf, eds.), Kluwer Academic, 1987, pp. 57 - 103
• C. J. Terman, "Timing Simulation for Large Digital MOS Circuits," in Advances in Computer-Aided Engineering, (A. Sangiovanni-Vincentelli, ed.), JAI Press, 1984, pp. 1 - 91
• C. J. Terman, Simulation Tools for Digital LSI Design, M.I.T. Laboratory for Computer Science Technical Report TR-304, September 1983, 158 pages
• C. J. Terman, The Specification of Code Generation Algorithms, M.I.T. Laboratory for Computer Science Technical Report TR-199, January 1978, 86 pages

• B. Ackland, A. Anesko, D. Brinthaupt, S. J. Daubert, A. Kalavade, J. Knobloch, E. Micca, M. Moturi, C. J. Nicol, J. H. O'Neill, J. Othmer, E. Sackinger, K. J. Singh, J. Sweet, C. J. Terman, J. Williams, "A Single-Chip 1.6 Billion 16-b MAC/s Multiprocessor DSP," IEEE Journal of Solid-State Circuits, Vol. 35, No. 3, March 2000, pp. 412 - 424
• J. Allen, C. J. Terman, "An Interactive Learning Environment for VLSI Design," Proceedings of the IEEE, Vol. 88, No. 1, January 2000, pp. 96 - 106
• M. Hostetter, D. Kranz, C. Seed, C. Terman, S. Ward, "Curl: A Gentle-slope Language for the Web," World Wide Web Journal, Vol. 2, No. 2, Spring 1997, pp. 121 - 134
• C. M. Baker, C. J. Terman, "Tools for Verifying Integrated Circuit Designs," Lambda Magazine (VLSI Design), 4th Quarter 1980, pp. 22 - 30
• C. S. Gillmor, C. J. Terman. "Communications Modes in Geophysics: The Case of Ionospheric Physics," EOS (Transactions of the American Geophysical Union), Vol. 54, No. 10, October 1973, pp. 900 - 908

• Hubert Pham, Justin Mazzola Paluska, Umar Saif, Chris Stawarz, Chris Terman, Steve Ward, "A Dynamic Platform for Runtime Adaptation", IEEE International Conference on Pervasive Computing and Communications (PerCom 2009)
• Justin Mazzola Paluska, Hubert Pham, Umar Saif, Chris Terman, Grace Chau, and Steve Ward, "Structured Decomposition of Adaptive Applications," IEEE International Conference on Pervasive Computing and Communications (PerCom 2008) [Best Paper Award]
• Umar Saif, Hubert Pham, Justin Mazzola Paluska, Jason Waterman, Chris Terman, Steve Ward, "A Case for Goal-oriented Programming Semantics," System Support for Ubiquitous Computing Workshop at the Fifth Annual Conference on Ubiquitous Computing (UbiComp '03)
• B. Ackland, A. Anesko, D. Brinthaupt, S. J. Daubert, A. Kalavade, J. Knobloch, E. Micca, M. Moturi, C. J. Nicol, J. H. O'Neill, J. Othmer, E. Sackinger, K. J. Singh, J. Sweet, C. J. Terman, J. Williams, "A Single-Chip 1.6 Billion 16-b MAC/s Multiprocessor DSP," IEEE Custom Integrated Cicuits Conference, San Diego, CA, May 1999, pp. 537 - 540
• J. Allen, C. J. Terman, "An Interactive Learning Environment for VLSI Design," 6th IEEE International Conference on Electronics, Circuits and Systems, Pafos, Cyprus, September 1999, pp. 1605 - 1610
• D. Brinthaupt, L. Letham, V. Maheshwari, J. Other, R. Spiwak, B. Edwards, C. Terman, N. Weste, "A Video Decoder for H.261 Video Teleconferencing and MPEG Stored Interactive Video Applications," IEEE International Solid-State Circuits Conference, 1993, pp. 34 - 35
• N. Weste, C. J. Terman, et al. "The Symbolics Ivory Design and Verification Strategy," IEEE International Conference on Computer Design: VLSI in Computers, October 1987
• J. Arnold, C. J. Terman, "A Multiprocessor Implementation of a Logic-level Timing Simulator," IEEE International Conference on Computer-Aided Design, November 1985, pp. 116 - 118
• C. J. Terman, "RSIM -- A Logic-level Timing Simulator," IEEE International Conference on Computer Design: VLSI in Computers, October 1983, pp. 437 - 440
• S. Ward, C. J. Terman, "An Approach to Personal Computing," IEEE Computer Society International Confereence (COMPCON), February 1980, pp. 460 - 465
• C. J. Terman, "Compiling Programs to Meet Real-time Constraints," Seventh Texas Conference on Computing Systems, October 1978, pp. 5-19 - 5-25