Load Instruction
ALU
Instruction
Memory
A
D
Data
Memory
A
RD
WD
R/W
A
B
Register
File
RA1
RD1
RD2
RA2
WE
WD
WA
+4
PC
Control
Logic
BSELWDSELALUFN
Wr
WERF
1
0
0
1
2
<PC> + 4
Wr
WERF
BSEL
WDSEL
ALUFN
00
raង:16>
rb:11>
rcញ:21>
C:0>
LD: rc MEM[<ra> + C ]
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