Branch Delay Slots
Problem: One (or more) following instructions have been prefetched by the time a branch is taken.
Possible solutions are
- “Program around it”
- Follow each branch instruction with a NOP = ADD(r31, r31, r31) instruction.
- Make the compiler clever enough to move useful instructions after branches. These instructions will be executed regardless of whether the branch is taken or not.
- Make pipeline “annul” instruction following branch which is taken, e.g., by disabling RF write and Memory write.