Pipelined b Processor Subtleties


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Table of Contents

Pipelined b Processor Subtleties

Recap: 4-Stage b Pipeline

Recap: Branch Hazards

Recap: Data Hazards


Bypass Paths

Load Timing

5-Stage Pipeline

5-Stage b Pipeline

Branch Delay Slots

Annulling Prefetched Instructions

Branch Decision Timing

Linkage Register Write Timing

Branch Destination Bypass - I

Branch Destination Bypass - II



Illegal Opcode Traps

Illegal Opcode Traps in b Pipeline

Next Time: Computer Arithmetic

Author: Srinivas Devadas

Email: devadas@mit.edu

Home Page: http://cag-www.lcs.mit.edu/6.004

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