Recap: Branch Hazards
Instruction
Memory
A
D
Register
File
RA1
RD1
RD2
RA2
+4
+
PCIF
0
1
4 3 2 1 0
RA2SEL
Z
00
<PC> + 4
+ 4C
C:0>
<ɚ
PCRF
IRRF
IF
RF
PCSEL
PCIF will have the correct address only in the i + 5 clock cycle, not i + 4
BNE
XOR
CMP
SUB
BNE
?
CMP
SUB
BNE
CMP
SUB
BNE
CMP
SUB
BNE
i
i + 1
i + 2
i + 3
i + 4
i + 5
i + 6
IF
RF
WB
ADD
ADD
ADD
ADD
ALU
Previous slide
Next slide
Back to first slide
View graphic version