Bypass Paths
ALU
Data
Memory
A
RD
WD
R/W
A
B
Register
File
RA1
RD1
RD2
RA2
1
0
1
0
0
1
0
1
2
RA2SEL
BSEL
ASEL
0
1
Register
File
WA
WD
WERF
IRRF
IRALU
A
B
IRWB
Y
DALU
DWB
LD(r1, 0, r4)
ADD(r1, r4, r5)
XOR(r3, r4, r6)
Above bypass will work for Problem 2
will not work for Problem 1
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