Load Timing
Fact: Processors will become faster relative to memories!
- Do we just lengthen the cycle time?
- Alternative: Longer pipelines
Longer pipelines by:
- Add “Memory Wait” stages between start of read operation and return of data.
- Build pipelined memories, so that multiple memory transactions can be in progress at once.
Read access time for:
- 4-Stage pipeline: 1 clock
- 5-Stage pipeline: 2 clocks