5-Stage b Pipeline
ALU
Instruction
Memory
A
D
Data Memory
A
RD
WD
R/W
A
B
Register
File
RA1
RD1
RD2
RA2
+4
+
PCIF
1
0
1
0
0
1
0
1
2
4 3 2 1 0
RA2SEL
BSEL
ASEL
WDSEL
ALUFN
PCSEL
Z
JT
00
<PC> + 4
+ 4C
raង:16>
rb:11>
rcញ:21>
C:0>
<ɚ
JT
ILL
OP
XAdr
0
1
WASEL
Register
File
WA
WD
WERF
C:0>
PCRF
IRRF
PCALU
IRALU
A
B
PCMEM
IRMEM
YMEM
DALU
DMEM
XP
rcញ:21>
IF
RF
ALU
WB
Omits some detail
No bypass or interlock logic
PCWB
IRWB
YWB
MEM
Wr
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