Branch Delay Slots
ADD
BNE
XORC
ADD
BNE
XORC
ADD
BNE
XORC
ADD
BNE
XORC
IF
RF
MEM
ADD
ADD
ADD
ADD
BNE
XORC
BNE
XORC
BNE
ALU
XORC
ADD
BNE
WB
i
i + 1
i + 2
i + 3
i + 4
i + 5
i + 6
Branch Decision Time
IF
instruction
instruction
instruction
instruction
RF
(read)
ALU
CL
A
B
Y
CL
CL
Instruction
Fetch
Register
File
ALU
Memory
Wait
RF
(write)
CL
Write
Back
Y
if <ra> = 0
branch
XORC being fetched
BNE
Previous slide
Next slide
Back to first slide
View graphic version