Branch Decision Timing
IF
instruction
instruction
instruction
instruction
RF
(read)
ALU
CL
A
B
Y
CL
CL
Instruction
Fetch
Register
File
ALU
Memory
Wait
RF
(write)
CL
Write
Back
Y
if (<ra> - <rb>) > 0
branch
Will have
branch delay slots
and instructions
to annul.
Architectural issue:
Simple branch condition logic, e.g., test if <ra> = 0.Decision in RF stage.
More powerful Compare-and-Branch instructions, e.g., test if <ra> > <rb>. Decision in ALU stage.
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