b Implementation
ALU
Instruction
Memory
A
D
Data
Memory
A
RD
WD
R/W
A
B
Register
File
RA1
RD1
RD2
RA2
WE
WD
WA
+4
+
PC
Control
Logic
PCSEL
RA2SEL
ASEL
BSELWDSELALUFN
Wr
WERF
WASEL
1
0
1
0
0
1
2
4 3 2 1 0
1
0
<PC> + 4
Wr
WERF
RA2SEL
BSEL
ASEL
WDSEL
WASEL
ALUFN
PCSEL
Z
JT
XP
00
<PC> + 4 +4 C
raង:16>
rb:11>
rcញ:21>
C:0>
<ɚ
rcញ:21>
C:0>
JT
ILL
OP
XAdr
Z
IRQ
sign extended
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