Pipelined b TLB Miss

ALU

Instruction

Memory

A

D

A

B

Register

File

RA1

RD1

RD2

RA2

+4

PCIF

4 3 2 1 0

ALUFN

00

JT

ILL

OP

XAdr

PCRF

IRRF

PCALU

IRALU

A

B

PCMEM

IRMEM

YMEM

PCWB

IRWB

YWB

TLB

miss

0

1

2

AnnulIF

NOP

BNE(r31, 0, XP)

1

0

1

0

AnnulALU

AnnulMEM

NOP

1

0

AnnulRF

NOP

VIRTUAL

MEMORY

ADDRESS

2

TLB miss?

Stall (freeze) pipeline

on a TLB miss until

Main Memory Page

Table is accessed

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