Cache State Transition Diagram
M: Modified Exclusive
E: Exclusive, unmodified
S: Shared
I: Invalid
M
E
S
I
Each cache line tag
Address tag
state
bits
Write miss
Other processor
intent to write
Read
miss
M1 intent to write
Other processor
intent to write
M1 write
Read by any
processor
M1 write
or read
Other processor
read/ Write back line
M1 read
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