Load Bypass Paths
ALU
Data
Memory
A
RD
WD
R/W
A
B
Register
File
RA1
RD1
RD2
RA2
1
0
1
0
0
1
2
RA2SEL
BSEL
ASEL
0
1
Register
File
WA
WD
WERF
IRRF
IRALU
A
B
IRWB
Y
DALU
DWB
LD(r31, Y, r2)
ADD(r1, r2, r3)
SUB(r1, r2, r4)
Even with full bypassing we need
cycle(s) of stalling between
LD(r31, Y, r2) and ADD(r1, r2, r3)
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