MASSACHUSETTS INSTITUTE OF TECHNOLOGY
School of Engineering Faculty Personnel Record

Date: May 2003  Full Name: Srinivas Devadas
   Department: Electrical Engineering
   and Computer Science

1. Education:

School Degree Date
I.I.T. Madras, India B.Tech. December 1984
University of California, Berkeley M.S. December 1986
University of California, Berkeley Ph.D. August 1988

2. Title of Thesis for Most Advanced Degree:

Techniques for Optimization-Based Synthesis of Digital Systems

3. Principal Fields of Interest:

All aspects of Computer-Aided Design (CAD) of VLSI computing systems, including optimization techniques for synthesis at the layout, logic, and architectural levels. Validation, including formal verification and manufacture test, of VLSI systems. Low-energy computing and low-power design. Computer architecture, in particular, memory system design and organization in high-performance computers, and architectural synthesis of embedded processors. Computer security, in particular, security issues in pervasive computing, and secure computer architectures.

4. Name and Rank of Other Department Faculty in the Same Field:

Anant Agarwal, Professor

Arvind, Professor

Daniel Jackson, Associate Professor

Charles Leiserson, Professor

Ronald Rivest, Professor

Jacob White, Professor

5. Name and Rank of Faculty in Other Departments in the Same Field:

F. Thomson Leighton, Professor of Mathematics

6. Non-MIT Experience (including military service):

Employer Position Beginning Ending
Univ. California Teaching Asst. Jan. 1985 May 1985
Univ. California Research Asst. June 1985 July 1986
D.E.C. Summer Res. Staff July 1986 Aug. 1986
Univ. California Research Asst. Aug. 1986 July 1988
Sandburst Corporation Principal Engineer September 2000 August 2001

7. History of MIT Appointments:

Rank Beginning Ending
Assistant Professor August 1988 June 1992
Associate Professor (without tenure) July 1992 June 1995
Associate Professor (with tenure) July 1995 June 1999
Professor July 1999 --

8. Consulting Record:

Firm Beginning Ending
AT&T Bell Labs (Murray Hill, NJ) Oct. 1989 September 1990
Synopsys, Inc. (Mountain View, CA) June 1991 September 1998
DynaLogic (Sunnyvale, CA) Technical Advisory Board July 1994 July 1998
Synopsys, Inc. (Marboro, MA) August 1999 January 2000
0-in Design Automation (San Jose, CA) Technical Advisory Board July 1996 --
Tioga Tech (San Jose, CA) Technical Advisory Board July 1999 June 2001
Sandburst Corporation (Andover, CA) September 2001 --

9. Department and Institute Committees, Other Assigned Duties:

Activity Beginning Ending
Undergraduate Counselor (Dept.) September 1989 August 1993
VI-A Representative, Schlumberger ATE February 1991 February 1997
Graduate Counselor (Dept.) September 1992 --
Graduate Admissions (Dept.) December 1993 July 1994
Graduate Admissions (Dept.) December 1995 July 2000
VI-A Representative, Teradyne February 1997 February 1998
VI-A Representative, Synopsys March 1998 --
Graduate Admissions (Dept.) December 2002 --
Area II Chair (Dept.) June 2003 --

10. Committees, Service, etc.:

Associate Editor, ACM Transactions on Design Automation of
Electronic Systems, 1997-99.
Editorial Board, Design Automation of Embedded
Systems: An Int'l Journal, 1996-present.
Editorial Board, Formal Methods in VLSI Design: An Int'l Journal 1992-present.
Guest Editor, Journal of Electronic Testing: Theory and Applications 1993.

General Co-Chair, ACM Joint LCTES/SCOPES Conference, 2002.
Tech. Program Comm. Chair, VLSI'99 1999.

Tech. Program Comm., MICRO-35, 2002.
Tech. Program Comm., Int'l Conference on Supercomputing, 2002.
Tech. Program Comm., CASES 2000.
Tech. Program Comm., Design Automation Conference 2000.
Tech. Program Comm., 20th Anniversary Conf. on Advanced Research in VLSI, 1999.
Tech. Program Comm., Int'l Conference on Computer-Aided Design, 1998.
Tech. Program Comm., Int'l Symposium on Low Power Design, 1995-97.
Tech. Program Comm., Int'l Conference on Computer Design 1990-94.
Tech. Program Comm., TAU'95 ACM Int'l Workshop on Timing Issues, 1995.
Tech. Program Comm., Asia South Pacific Design Automation Conference 1995.
Tech. Program Comm., Int'l Conference on Computer-Aided Design 1992-95.
Tech. Program Comm., European Design Automation Conference 1991-93.
Tech. Program Comm., CSI/IEEE Int'l Symposium on VLSI Design 1991-97.
Tech. Program Comm., Advanced Research in VLSI Conference 1992,95
Tech. Program Comm., Multi-Chip Module Conference 1992.

Tech. Program Comm., International Workshop on Software and Compilers
for Embedded Systems, 1998-00.
Tech. Program Comm., Int'l Workshop on Logic Synthesis 1991,95,97.
Tech. Program Comm., Int'l Workshop on Low Power Design, 1994.
Tech. Program Comm., IFIP Workshop on Control Dominated Synthesis
from a Register-Transfer Level Description 1992.
Tech. Program Comm., IFIP WG 10.5 Int'l Workshop on the
Relationship Between Synthesis, Test and Verification, 1991.
Tech. Program Comm., Int'l Workshop on Formal Methods in VLSI Design 1991.

11. Awards and Honors Received:

Fellow of the IEEE, 1998.

IASTED Int'l Conference on Parallel and Distributed Computing
and Systems Best Paper Award, High Performance Systems Category, 2001.
35th Design Automation Conference Best Paper Award, Design Methods Category, 1998.
1996 IEEE Transactions on VLSI Systems, Best Paper Award.
1992 Int'l Conference on Computer Design Best Paper Award, CAD Track.
1991 Int'l Conference on Computer-Aided Design Distinguished Paper Citation.
1990 IEEE Transactions on Computer-Aided Design, Best Paper Award.
27th Design Automation Conference Best Paper Award, Synthesis Category, 1990.
27th Design Automation Conference Best Paper Award, Test Category, 1990.

Schlumberger Foundation Grant, 1993, 1994, 1995.
National Science Foundation Young Investigator Award, 1992.
 
Analog Devices Career Development Chair, Mass. Instt. of Tech., 1989-91.
Philips Medal, Indian Institute of Technology, Madras, June 1985.

12. Current Organization Membership:

IEEE Fellow.
ACM Member.

13. Patents and Patent Applications Pending:

Simulation Vector Generation from HDL Descriptions for
Observability-Enhanced Statement Coverage, with P. Ashar and F. Fallah,
patent filed June 1999.


Method and Apparatus for Allocating Link Bandwidth,
with H. Balakrishnan and D. Rosenband, patent filed July 2001.


Authentication of Integrated Circuits,
with B. Gassend, M. van Dijk and D. Clarke, patent filed April 2003.

14. Professional Registration:

Teaching Experience of SRINIVAS DEVADAS

Term Subj. No. Title Role
FT88 6.002 Circuits and Electronics Recitations (2 sect.)
ST89 6.891 Computer-Aided Design of Integrated Circuits Lectures, development (with Prof. Jacob White)
FT89 6.371 Introduction to VLSI Systems Lectures
ST90 6.371 Introduction to VLSI Systems Lectures
ST91 6.891 Computer-Aided Design of Integrated Circuits Lectures
FT91 6.371 Introduction to VLSI Systems Lectures
ST92 6.892 Formal Verification in VLSI Design Lectures, development
FT92 6.004 Computation Structures Recitations (2 sect.)
ST93 6.373 Computer-Aided Design of Integrated Circuits Lectures
FT93 6.004 Computation Structures Recitations (2 sect.)
ST94 6.004 Computation Structures Recitations (2 sect.)
FT94 6.371 Introduction to VLSI Systems Lectures
ST95 6.373 Computer-Aided Design of Integrated Circuits Lectures
FT95 6.371 Introduction to VLSI Systems Lectures
FT96 6.004 Computation Structures Lectures
ST97 6.373 Computer-Aided Design of Integrated Circuits Lectures
FT97 6.371 Introduction to VLSI Systems Lectures
ST98 6.004 Computation Structures Lectures
Term Subj. No. Title Role
FT98 6.042J Mathematics for Computer Science Lectures (with Prof. Nancy Lynch)
ST99 6.373 Computer-Aided Design of Integrated Circuits Lectures
FT00 6.042J Mathematics for Computer Science Lectures (with Prof. Nancy Lynch)
FT01 6.170 Laboratory in Software Engineering Lectures (with Prof. Daniel Jackson)
ST02 6.170 Laboratory in Software Engineering Lectures (with Prof. John Guttag)
ST02 6.823 Computer Architecture Lectures (with Prof. Krste Asanovic)
ST03 6.042J Mathematics for Computer Science Lectures (with Prof. Charles Leiserson)

Publications of SRINIVAS DEVADAS

1. Books:

  1. Ashar, P., S. Devadas and A. R. Newton, ``Sequential Logic Synthesis'', Kluwer Academic Publishers, 1992.

  2. Ghosh, A., S. Devadas and A. R. Newton, ``Sequential Logic Testing and Verification'', Kluwer Academic Publishers, 1992.

  3. Devadas, S., A. Ghosh and K. Keutzer, ``Logic Synthesis'', McGraw Hill Series on Computer Engineering, McGraw Hill, 1994.

  4. Monteiro, J., and S. Devadas, ``Computer-Aided Design Techniques for Low Power Sequential Logic Circuits'', Kluwer Academic Publishers, 1997.

2. Papers in Refereed Journals:

  1. Devadas, S., and A. R. Newton, ``Topological Optimization of Multiple Level Array Logic'', IEEE Transactions on Computer-Aided Design, pages 915-942, Volume CAD-6, Number 6, November 1987.

  2. Devadas, S., H-K. T. Ma and A. R. Newton, ``On the Verification of Sequential Machines At Differing Levels of Abstraction'', IEEE Transactions on Computer-Aided Design, pages 713-722, Volume 7, Number 6, June 1988.

  3. Braun, D., J. Burns, S. Devadas, H-K. T. Ma, K. Mayaram, F. Romeo and A. Sangiovanni-Vincentelli, ``Techniques for Multi-Layer Channel Routing'', IEEE Transactions on Computer-Aided Design, pages 698-712, Volume 7, Number 6, June 1988.

  4. Ma, H-K. T., S. Devadas, A. R. Newton and A. Sangiovanni-Vincentelli, ``Test Generation for Sequential Circuits'', IEEE Transactions on Computer-Aided Design, pages 1081-1093, Volume 7, Number 10, October 1988.

  5. Devadas, S., H-K. T. Ma, A. R. Newton and A. Sangiovanni-Vincentelli, ``MUSTANG: State Assignment of Finite State Machines Targeting Multi-Level Logic Implementations'', IEEE Transactions on Computer-Aided Design, pages 1290-1300, Volume 7, Number 12, December 1988.

  6. Ma, H-K. T., S. Devadas, R-S. Wei and A. Sangiovanni-Vincentelli, ``Logic Verification Algorithms and Their Parallel Implementation'', IEEE Transactions on Computer-Aided Design, pages 181-189, Volume 8, Number 1, February 1989.

  7. Devadas, S., A. R. Wang, A. R. Newton and A. Sangiovanni-Vincentelli, ``Boolean Decomposition in Multi-Level Logic Optimization'', Journal of Solid State Circuits, pages 399-408, Volume 24, Number 2, April 1989.

  8. Devadas, S., and A. R. Newton, ``Algorithms for Hardware Allocation in Datapath Synthesis'', IEEE Transactions on Computer-Aided Design, pages 768-781, Volume 8, Number 7, July 1989.
  9. Devadas, S., H-K. T. Ma, A. R. Newton and A. Sangiovanni-Vincentelli, ``A Synthesis and Optimization Procedure for Fully and Easily Testable Sequential Machines'', IEEE Transactions on Computer-Aided Design, pages 1100-1107, Volume 8, Number 10, October 1989.

  10. Devadas, S. and A. R. Newton, ``Decomposition and Factorization of Sequential Finite State Machines'' IEEE Transactions on Computer-Aided Design, pages 1206-1217, Volume 8, Number 11, November 1989.
  11. Devadas, S., H-K. T. Ma, A. R. Newton and A. Sangiovanni-Vincentelli, ``Irredundant Sequential Machines Via Optimal Logic Synthesis'', IEEE Transactions on Computer-Aided Design, pages 8-18, Volume 9, Number 1, January 1990.

  12. Devadas, S., H-K. T. Ma and A. R. Newton, ``Redundancies and Don't Cares in Sequential Logic Synthesis'', Journal of Electronic Testing: Theory and Applications, pages 15-30, Volume 1, Number 1, February 1990.

  13. Devadas, S., ``Optimal Layout Via Boolean Satisfiability'', Int'l Journal of Computer-Aided VLSI Design, Volume 2, Number 2, pages 251-262, 1990.

  14. Devadas, S. and H-K. T. Ma, ``Easily Testable PLA-based Finite State Machines'', IEEE Transactions on Computer-Aided Design, pages 614-611, Volume 9, Number 6, June 1990.
  15. Devadas, S. and A. R. Newton, ``Exact Algorithms for Output Encoding, State Assignment and Four-Level Boolean Minimization'', IEEE Transactions on Computer-Aided Design, pages 13-27, Volume 10, Number 1, January 1991.

  16. Devadas, S. and K. Keutzer, ``A Unified Approach to the Synthesis of Fully Testable Sequential Machines'', IEEE Transactions on Computer-Aided Design, pages 39-50, Volume 10, Number 1, January 1991.

  17. Ashar, P., S. Devadas and A. R. Newton, ``Irredundant Interacting Sequential Machines Via Optimal Logic Synthesis'', IEEE Transactions on Computer-Aided Design, pages 311-325, Volume 10, Number 3, March 1991.

  18. Ashar, P., S. Devadas and A. R. Newton, ``Optimum and Heuristic Algorithms for a Problem of Finite State Machine Decomposition'', IEEE Transactions on Computer-Aided Design, pages 296-310, Volume 10, Number 3, March 1991.

  19. Ghosh, A., S. Devadas and A. R. Newton, ``Test Generation and Verification of Highly Sequential Circuits'', IEEE Transactions on Computer-Aided Design, pages 652-667, Volume 10, Number 5, May 1991.

  20. Devadas, S., ``Delay Test Generation for Synchronous Sequential Circuits'', Int'l Journal of Computer-Aided VLSI Design, Volume 3, Number 2, pages 173-192, June 1991.

  21. Devadas, S., ``Optimizing Interacting Finite State Machines Using Sequential Don't Cares'', IEEE Transactions on Computer-Aided Design, pages 1473-1484, Volume 10, Number 12, December 1991.

  22. Devadas, S. and K. Keutzer, ``An Automata-Theoretic Approach to Behavioral Equivalence'', INTEGRATION, The VLSI Journal, Volume 12, Number 2, pages 109-129, December 1991.
  23. Devadas, S. and K. Keutzer, ``Synthesis of Robust Delay-Fault Testable Circuits: Theory'', IEEE Transactions on Computer-Aided Design, pages 87-101, Volume 11, Number 1, January 1992.

  24. Devadas, S. and K. Keutzer, ``Synthesis of Robust Delay-Fault Testable Circuits: Practice'', IEEE Transactions on Computer-Aided Design, pages 277-300, Volume 11, Number 3, March 1992.

  25. Devadas, S., K. Keutzer and J. White, ``Estimation of Power Dissipation in CMOS Combinational Circuits Using Boolean Function Manipulation'', IEEE Transactions on Computer-Aided Design, pages 373-383, Volume 11, Number 3, March 1992.

  26. Ashar, P., A. Ghosh and S. Devadas, ``Boolean Satisfiability and Equivalence Checking Using General Binary Decision Diagrams'', INTEGRATION, The VLSI Journal, Volume 13, Number 1, pages 1-16, May 1992.

  27. Bryan, M. J., S. Devadas and K. Keutzer, ``Necessary and Sufficient Conditions for Hazard-Free Robust Transistor Stuck-Open Fault Testability in Multilevel Networks'', IEEE Transactions on Computer-Aided Design, pages 800-803, Volume 11, Number 6, June 1992.

  28. Ghosh, A., S. Devadas and A. R. Newton, ``Heuristic Minimization of Boolean Relations Using Testing Techniques'', IEEE Transactions on Computer-Aided Design, pages 1166-1172, Volume 11, Number 9, September 1992.

  29. Devadas, S. and K. Keutzer, ``Validatable Nonrobust Delay-Fault Testable Circuits Via Logic Synthesis'', IEEE Transactions on Computer-Aided Design, pages 1559-1573, Volume 11, Number 12, December 1992.

  30. Ashar, P., S. Devadas and K. Keutzer, ``Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks'', Formal Methods in VLSI Design: An International Journal, Volume 2, Number 1, pages 93-112, February 1993.

  31. Devadas, S., K. Keutzer and S. Malik, ``A Synthesis-Based Test Generation and Compaction Algorithm for Multifaults'', Journal of Electronic Testing: Theory and Applications, Volume 4, Number 1, pages 91-104, February 1993.

  32. Devadas, S., ``Microlectronic System Design Skills for the Year 2000 and Beyond'', Journal of Microlectronic System Integration, Volume 1, Number 1, pages 85-95, March 1993.

  33. Ghosh, A., S. Devadas and A. R. Newton, ``Sequential Test Generation and Synthesis for Testability at the Register-Transfer and Logic Levels'', IEEE Transactions on Computer-Aided Design, Volume 12, Number 5, pages 579-598, May 1993.

  34. Devadas, S., ``Comparing Two-Level and Ordered Binary Decision Diagram Representations of Logic Functions'', IEEE Transactions on Computer-Aided Design, Volume 12, Number 5, pages 722-723, May 1993.

  35. Jyu, H-F., S. Malik, S. Devadas and K. Keutzer, ``Statistical Timing Analysis of Combinational Logic Circuits'', IEEE Transactions on VLSI Systems, Volume 1, Number 2, pages 126-137, June 1993.

  36. Ashar, P., S. Devadas and K. Keutzer, ``Path-Delay-Fault Testability Properties of Multiplexor-Based Networks'' INTEGRATION, the VLSI Journal, Volume 15, Number 1, pages 1-23, July 1993.

  37. Bryan, M. J., S. Devadas and K. Keutzer, ``Analysis and Design of Regular Structures for Robust Dynamic Fault Testability'', VLSI Design: An International Journal of Custom-Chip Design, Simulation and Testing, Volume 1, Number 1, pages 45-60, August 1993.

  38. Cheng, K-T., S. Devadas and K. Keutzer, ``Robust Delay-Fault Test Generation and Synthesis for Testability Under a Standard Scan Design Methodology'', IEEE Transactions on Computer-Aided Design, Volume 12, Number 8, pages 1217-1232, August 1993.

  39. Liao S., and S. Devadas, ``Automatic Generation and Verification of Sufficient Correctness Properties for Synchronous Array Processors'', IEICE Transactions on Information and Systems, Volume E76-D, Number 9, pages 1030-1038, September 1993.
  40. Devadas, S., K. Keutzer and S. Malik, ``Computation of Floating Mode Delay in Combinational Logic Circuits: Theory and Algorithms'', IEEE Transactions on Computer-Aided Design, Volume 12, Number 12, pages 1913-1923, December 1993.

  41. Devadas, S., K. Keutzer, S. Malik and A. Wang, ``Computation of Floating Mode Delay in Combinational Logic Circuits: Practice and Implementation'', IEEE Transactions on Computer-Aided Design, Volume 12, Number 12, pages 1924-1936, December 1993.

  42. Van Aelten, F., J. Allen and S. Devadas, ``Verification of Relations Between Synchronous Machines'', IEEE Transactions on Computer-Aided Design, Volume 12, Number 12, pages 1947-1959, December 1993.
  43. Van Aelten, F., J. Allen and S. Devadas, ``Event-Based Verification of Synchronous Globally Controlled Logic Designs against Signal Flow Graphs'', IEEE Transactions on Computer-Aided Design, Volume 13, Number 1, pages 122-134, January 1994.

  44. Devadas, S., K. Keutzer, S. Malik and A. Wang, ``Verification of Asynchronous Interface Circuits with Bounded Wire Delays'', Journal of VLSI Signal Processing, Volume 7, Number 1, pages 161-182, March 1994.

  45. Devadas, S., K. Keutzer, S. Malik and A. Wang, ``Event Suppression: Improving the Efficiency of Timing Simulation for Synchronous Digital Circuits'', IEEE Transactions on Computer-Aided Design, Volume 13, Number 6, pages 814-822, June 1994.

  46. Devadas, S., K. Keutzer, S. Malik and A. Wang, ``Certified Timing Verification and the Transition Delay of a Circuit'', IEEE Transactions on VLSI Systems, Volume 2, Number 3, pages 333-342, September 1994.
  47. Alidina, M., José Monteiro, S. Devadas, A. Ghosh and M. Papaefthymiou, ``Precomputation-Based Sequential Logic Optimization for Low Power'', IEEE Transactions on VLSI Systems, Volume 2, Number 4, pages 426-436, December 1994.

  48. Shen, A., S. Devadas and A. Ghosh, ``Probabilistic Manipulation of Boolean Functions Using Free Boolean Diagrams'', IEEE Transactions on Computer-Aided Design, Volume 14, Number 1, pages 87-95, January 1995.

  49. Lin, B., and S. Devadas, ``Synthesis of Hazard-Free Multilevel Logic Under Multiple-Input Changes from Binary Decision Diagrams'', IEEE Transactions on Computer-Aided Design, Volume 14, Number 8, pages 974-985, August 1995.
  50. Tsui, C-Y., J. Monteiro, M. Pedram, S. Devadas, A. M. Despain, and B. Lin, ``Power Estimation Methods for Sequential Logic Circuits'', IEEE Transactions on VLSI Systems, Volume 3, Number 3, pages 404-416, September 1995.

  51. Monteiro, J., S. Devadas, and A. Ghosh, ``Retiming Sequential Circuits for Low Power'', International Journal of High-Speed Electronics and Systems, Volume 7, Number 2, pages 323-340, May 1996.

  52. Liao, S., S. Devadas, K. Keutzer, S. Tjiang and A. Wang, ``Storage Assignment to Decrease Code Size'', ACM Transactions on Programming Languages and Systems, Volume 18, Number 3, pages 235-253, May 1996.

  53. Monteiro, J., and S. Devadas, ``Techniques for Power Estimation and Optimization at the Logic Level: A Survey'', Journal of VLSI Signal Processing, Volume 13, Numbers 2/3, pages 259-276, August/September 1996.
  54. Monteiro, J., S. Devadas, A. Ghosh, K. Keutzer, and J. White, ``Estimation of Average Switching Activity in Combinational Logic Circuits Using Symbolic Simulation'', IEEE Transactions on Computer-Aided Design, Volume 16, Number 1, pages 121-127, January 1997.

  55. Liao, S., S. Devadas, K. Keutzer, S. Tjiang and A. Wang, ``Code Optimization Techniques in Embedded DSP Processors'', Design Automation of Embedded Systems: An International Journal, Volume 3, Number 1, pages 59-74, January 1998.

  56. Hadjiyiannis, G., A. P. Chandrakasan and S. Devadas, ``A Low-Power, Low-Bandwidth Protocol for Remote Wireless Terminals'', ACM Transactions on Wireless Networks, Volume 4, Number 1, pages 3-15, 1998.

  57. Liao, S., K. Keutzer, S. Tjiang, and S. Devadas, ``A New Viewpoint on Code Generation for Directed Acyclic Graphs'', ACM Transactions on Design Automation of Electronic Systems, Volume 3, Number 1, pages 51-75, January 1998.

  58. Monteiro, J., S. Devadas and A. Ghosh, ``Sequential Logic Optimization for Low Power Using Input-Disabling Precomputation Architectures'', IEEE Transactions on Computer-Aided Design, Volume 17, Number 3, pages 279-284, March 1998.

  59. Monteiro, J. and S. Devadas, ``Power Estimation Under User-Specified Input Sequences and Programs'', Integrated Computer-Aided Engineering, Volume 5, Number 2, pages 177-185, April 1998.

  60. Liao, S., S. Devadas and K. Keutzer, ``Code Density Optimization for Embedded DSP Processors Using Data Compression Techniques'', IEEE Transactions on Computer-Aided Design, Volume 17, Number 7, pages 601-608, July 1998.

  61. Yun, K., B. Lin, D. Dill and S. Devadas, ``BDD-Based Synthesis of Extended Burst-Mode Controllers'', IEEE Transactions on Computer-Aided Design, Volume 17, Number 9, pages 782-792, September 1998.

  62. Liao, S., S. Devadas and K. Keutzer, ``A Text-Compression-Based Method for Code Size Minimization in Embedded Systems'', ACM Transactions on Design Automation of Electronic Systems, Volume 4, Number 1, pages 12-38, January 1999.

  63. Sudarsanam, A., S. Liao and S. Devadas, ``Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Processors and ASIPs'', Design Automation of Embedded Systems: An International Journal, Volume 4, Number 1, pages 5-22, January 1999.

  64. Fallah, F., S. Liao and S. Devadas, ``Solving Covering Problems Using LPR-Based Lower Bounds'', IEEE Transactions on VLSI Systems, Volume 8, Number 1, pages 9-17, February 2000.

  65. Hadjiyiannis, G., S. Hanono and S. Devadas, ``ISDL: An Instruction Set Description Language for Retargetability and Architecture Exploration'', Design Automation for Embedded Systems, Volume 6, pages 39-69, 2000.

  66. Fallah, F., S. Devadas, and K. Keutzer, ``Functional Test Generation Using Linear Programming and 3-Satisfiability'', IEEE Transactions on Computer-Aided Design, Volume 20, Number 8, pages 994-1002, August 2001.

  67. Fallah, F., S. Devadas, and K. Keutzer, ``OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Simulation'', IEEE Transactions on Computer-Aided Design, Volume 20, Number 8, pages 1003-1015, August 2001.

  68. Hadjiyiannis, G., and S. Devadas, ``Techniques for Accurate Performance Evaluation in Architecture Exploration'', IEEE Transactions on VLSI Systems, to appear in 2003.

  69. Suh, E. G., L. Rudolph, and S. Devadas, ``Dynamic Cache Partitioning for CMP Systems'', Journal of Supercomputing, to appear in 2003.

  70. Fallah, F., S. Devadas, and P. Ashar, ``Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage'', IEEE Transactions on VLSI Systems, to appear in 2003.

3. Proceedings of Refereed Conferences:

  1. Devadas, S. and A. R. Newton, ``GENIE: A Generalized Array Optimizer for VLSI Synthesis'', Proceedings of 23rd Design Automation Conference, pages 631-637, Las Vegas, July 1986.

  2. D. Braun, J. Burns, S. Devadas, H-K. T. Ma, K. Mayaram, F. Romeo and A. Sangiovanni-Vincentelli, ``CHAMELEON: A New Multi-layer Channel Router", Proceedings of 23rd Design Automation Conference, pages 495-502, Las Vegas, July 1986.

  3. Devadas, S. and A. R. Newton, ``Topological Optimization of Multiple Level Array Logic: On Uni and Multi-Processors'', Proceedings of Int'l Conference on Computer-Aided Design, pages 38-42, Santa Clara, November 1986.

  4. Devadas, S. and A. R. Newton, ``Data Path Synthesis from Behavioral Descriptions: An Algorithmic Approach'', Proceedings of Int'l Conference on Circuits and Systems, pages 398-401, Philadelphia, May 1987.

  5. Devadas, S., H-K. T. Ma and A. R. Newton, ``On the Verification of Sequential Machines At Differing Levels of Abstraction'', Proceedings of 24th Design Automation Conference, pages 271-276, Miami Beach, June 1987.

  6. H-K. T. Ma, S. Devadas, A. Sangiovanni-Vincentelli and R-S. Wei, ``Logic Verification Algorithms and their Parallel Implementation'', Proceedings of 24th Design Automation Conference, pages 283-290, Miami Beach, June 1987.

  7. Devadas, S. and A. R. Newton, ``Algorithms for Hardware Allocation in Datapath Synthesis'', Proceedings of Int'l Conference on Computer Design: VLSI in Computers, pages 526-531, New York, October 1987.

  8. H-K. T. Ma, S. Devadas, A. R. Newton and A. Sangiovanni-Vincentelli, ``Test Generation for Sequential Finite State Machines'', Proceedings of Int'l Conference on Computer-Aided Design, pages 288-291, Santa Clara, November 1987.

  9. Devadas, S., H-K. T. Ma, A. R. Newton and A. Sangiovanni-Vincentelli, ``MUSTANG: State Assignment of Finite State Machines for Optimal Multi-Level Logic Implementations'', Proceedings of Int'l Conference on Computer-Aided Design, pages 16-19, Santa Clara, November 1987.

  10. Devadas, S., A. R. Wang, A. R. Newton and A. Sangiovanni-Vincentelli, ``Boolean Decomposition of Programmable Logic Arrays'', Proceedings of Custom Integrated Circuits Conference, pages 2.5.1-2.5.5, Rochester, May 1988.

  11. Devadas, S., H-K. T. Ma, A. R. Newton and A. Sangiovanni-Vincentelli, ``Synthesis and Optimization Procedures for Fully and Easily Testable Sequential Machines'', Proceedings of Int'l Test Conference, pages 621-630, Washington D. C., September 1988.

  12. H-K. T. Ma, S. Devadas, A. R. Newton and A. Sangiovanni-Vincentelli, ``An Incomplete Scan Design approach to Test Generation for Sequential Circuits'', Proceedings of Int'l Test Conference, pages 730-734, Washington D. C., September 1988.

  13. Devadas, S., H-K. T. Ma, A. R. Newton and A. Sangiovanni-Vincentelli, ``Optimal Logic Synthesis and Testability: Two Faces of the Same Coin'', Proceedings of Int'l Test Conference, pages 4-12, Washington D. C., September 1988.

  14. Devadas, S., A. R. Wang, A. R. Newton and A. Sangiovanni-Vincentelli, ``Boolean Decomposition in Multi-Level Logic Optimization'', Proceedings of Int'l Conference on Computer-Aided Design, pages 148-151, Santa Clara, November 1988.

  15. Devadas, S. and A. R. Newton, ``Decomposition and Factorization of Sequential Finite State Machines'', Proceedings of Int'l Conference on Computer-Aided Design, pages 290-293, Santa Clara, November 1988.

  16. Devadas, S., ``General Decomposition of Sequential Machines: Relationships to State Assignment'', Proceedings of 26th Design Automation Conference, pages 314-320, Las Vegas, June 1989.

  17. Devadas, S., ``Approaches to Multi-Level Sequential Logic Synthesis'', Proceedings of 26th Design Automation Conference, pages 270-276, Las Vegas, June 1989.

  18. Devadas, S., H-K. T. Ma and A. R. Newton, ``Easily Testable PLA-based Finite State Machines'', Proceedings of 19th Fault Tolerant Computing Symposium, pages 102-109, Chicago, June 1989.

  19. Devadas, S., H-K. T. Ma and A. R. Newton, ``Redundancies and Don't Cares in Sequential Logic Synthesis'', Proceedings of Int'l Test Conference, pages 490-500, Washington D. C., August 1989.

  20. Devadas, S., ``Delay Test Generation for Synchronous Sequential Circuits'', Proceedings of Int'l Test Conference, pages 144-152, Washington D. C., August 1989.

  21. Devadas, S., H-K. T. Ma, A. R. Newton and A. Sangiovanni-Vincentelli, ``The Relationship Between Logic Synthesis and Test'', Proceedings of VLSI 89, pages 175-186, Munich, August 1989.

  22. Devadas, S. and K. Keutzer, ``Boolean Minimization and Algebraic Factorization Procedures for Fully Testable Sequential Machines'', Proceedings of Int'l Conference on Computer-Aided Design, pages 208-211, Santa Clara, November 1989.

  23. Ashar, P., S. Devadas and A. R. Newton, ``Optimum and Heuristic Algorithms for Finite State Machine Decomposition and Partitioning'', Proceedings of Int'l Conference on Computer-Aided Design, pages 216-219, Santa Clara, November 1989.

  24. Ghosh, A., S. Devadas and A. R. Newton, ``Test Generation for Highly Sequential Circuits'', Proceedings of Int'l Conference on Computer-Aided Design, pages 362-365, Santa Clara, November 1989.

  25. Devadas, S., ``Optimal Layout Via Boolean Satisfiability'', Proceedings of Int'l Conference on Computer-Aided Design, pages 294-297, Santa Clara, November 1989.

  26. Devadas, S., H-K. T. Ma, A. R. Newton and A. Sangiovanni-Vincentelli, ``Irredundant Sequential Machines Via Optimal Logic Synthesis'', Proceedings of 23rd Hawaii International Conference on System Sciences, pages 417-426, Kona, January 1990.

  27. Devadas, S. and A. R. Newton, ``Exact Algorithms of Output Encoding, State Assignment and Four-Level Boolean Minimization'', Proceedings of 23rd Hawaii International Conference on System Sciences, pages 387-396, Kona, January 1990.

  28. Devadas, S. and K. Keutzer, ``A Unified Approach to the Synthesis of Fully Testable Sequential Machines'', Proceedings of 23rd Hawaii International Conference on System Sciences, pages 427-435, Kona, January 1990.

  29. Devadas, S. and K. Keutzer, ``Necessary and Sufficient Conditions for Robust Delay-Fault Testability of Logic Circuits'', Proceedings of the Sixth MIT Conference on Advanced Research in VLSI, pages 221-238, Cambridge, April 1990.

  30. Ashar, P., S. Devadas, A. R. Newton, ``Multiple-Fault Testable Sequential Machines'', Proceedings of the Int'l Conference on Circuits and Systems, pages 3118-3121, New Orleans, May 1990.

  31. Lam, K., and S. Devadas, ``Performance-Oriented Synthesis of Finite State Machines'', Proceedings of the Int'l Conference on Circuits and Systems, pages 2642-2645, New Orleans, May 1990.

  32. Devadas, S. and K. Keutzer, ``Synthesis for Testability: A Brief Survey'', Proceedings of the Int'l Conference on Circuits and Systems, pages 3097-3100, New Orleans, May 1990.

  33. Devadas, S. and K. Keutzer, ``Validatable Nonrobust Delay-Fault Testable Circuits Via Logic Synthesis'', Proceedings of the Int'l Conference on Circuits and Systems, pages 3109-3113, New Orleans, May 1990.

  34. Devadas, S., K. Keutzer and J. White, ``Estimation of Power Dissipation in CMOS Combinational Circuits'', Proceedings of the Custom Integrated Circuits Conference, pages 19.7.1-19.7.6, Boston, May 1990.

  35. Devadas, S., ``Minimization of Functions with Multiple-Valued Outputs: Theory and Applications'', Proceedings of the 20th Int'l Symposium on Multiple-Valued Logic, pages 308-315, Charlotte, May 1990.

  36. Ghosh, A., S. Devadas and A. R. Newton, ``Verification of Interacting Sequential Circuits'', Proceedings of the 27th Design Automation Conference, pages 213-219, Orlando, June 1990.

  37. Ghosh, A., S. Devadas and A. R. Newton, ``Sequential Test Generation at the Register-Transfer and Logic Levels'', Proceedings of the 27th Design Automation Conference, pages 580-586, Orlando, June 1990.

  38. Ashar, P., S. Devadas and A. R. Newton, ``A Unified Approach to the Decomposition and Re-Decomposition of Sequential Machines'', Proceedings of the 27th Design Automation Conference, pages 601-606, Orlando, June 1990.

  39. Devadas, S. and K. Keutzer, ``Synthesis and Optimization Procedures for Robustly Delay-Fault Testable Logic Circuits'', Proceedings of the 27th Design Automation Conference, pages 221-227, Orlando, June 1990.

  40. Ashar, P., S. Devadas and A. R. Newton, ``Testability-Driven Synthesis of Interacting Finite State Machines'', Proceedings of the Int'l Conference on Computer Design: VLSI in Computers and Processors, pages 273-276, Cambridge, September 1990.

  41. Ghosh, A., S. Devadas and A. R. Newton, ``Heuristic Minimization of Boolean Relations Using Testing Techniques'', Proceedings of the Int'l Conference on Computer Design: VLSI in Computers and Processors, pages 276-280, Cambridge, September 1990.

  42. Ghosh, A., S. Devadas and A. R. Newton, ``Synthesis for Sequential Logic Testability at the Register-Transfer Level'', Proceedings of the Int'l Test Conference, pages 274-283, Washington D.C., September 1990.

  43. Devadas, S. and K. Keutzer, ``Design of Integrated Circuits Fully Testable for Delay-Faults and Multifaults'', Proceedings of the Int'l Test Conference, pages 284-293, Washington D.C., September 1990.

  44. Ashar, P., A. Ghosh, S. Devadas and A. R. Newton, ``Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test'', Proceedings of the Int'l Conference on Computer-Aided Design, pages 84-87, Santa Clara, November 1990.

  45. Bryan, M. J., S. Devadas and K. Keutzer, ``Testability-Preserving Circuit Transformations'', Proceedings of the Int'l Conference on Computer-Aided Design, pages 456-459, Santa Clara, November 1990.

  46. Devadas, S. and K. Keutzer, ``An Automata-Theoretic Approach to Behavioral Equivalence'', Proceedings of the Int'l Conference on Computer-Aided Design, pages 30-33, Santa Clara, November 1990.

  47. Ashar, P., S. Devadas and K. Keutzer, ``Testability Properties of Multilevel Logic Networks Derived from Binary Decision Diagrams'', Proceedings of Conference on Advanced Research in VLSI, pages 35-54, Santa Cruz, March 1991.

  48. Devadas, S., K. Keutzer and A. Ghosh, ``Recent Progress in VLSI Synthesis for Testability'', Proceedings of the VLSI Test Symposium, pages 22-29, Atlantic City, April 1991.

  49. Bryan, M. J., S. Devadas and K. Keutzer, ``Analysis and Design of Regular Structures for Robust Dynamic Fault Testability'', Proceedings of the Int'l Symposium on Circuits and Systems, pages 2644-2648, Singapore, June 1991.

  50. Ghosh A., and S. Devadas, ``Implicit Depth-First Traversal of Sequential Machines'', Proceedings of the Int'l Symposium on Circuits and Systems, pages 3102-3105, Singapore, June 1991. Also in the Proceedings of the Int'l Workshop on Logic Synthesis, Volume 3, paper 9.2b, Raleigh, May 1991.

  51. Devadas, S., K. Keutzer and S. Malik, ``A Synthesis-Based Approach to Test Generation and Compaction for Multifaults'', Proceedings of the 28th Design Automation Conference, pages 359-365, San Francisco, June 1991.

  52. Cheng, K-T., S. Devadas and K. Keutzer, ``Robust Delay Fault Test Generation and Synthesis for Testability Under a Standard Scan Design Methodology'', Proceedings of the 28th Design Automation Conference, pages 80-86, San Francisco, June 1991.

  53. Devadas, S., K. Keutzer and A. S. Krishnakumar, ``Design Verification and Reachability Analysis Using Algebraic Manipulation'', Proceedings of the Int'l Conference on Computer Design: VLSI in Computers and Processors, pages 250-258, Cambridge, October 1991.

  54. Ashar, P., S. Devadas and A. Ghosh, ``Boolean Satisfiability and Equivalence Checking Using General Binary Decision Diagrams'', Proceedings of the Int'l Conference on Computer Design: VLSI in Computers and Processors, pages 259-264, Cambridge, October 1991.

  55. Ashar, P., S. Devadas and K. Keutzer, ``Gate-Delay-Fault Testability Properties of Multiplexor-Based Logic Networks'', Proceedings of the Int'l Test Conference, pages 887-896, Nashville, October 1991.

  56. Cheng, K-T., S. Devadas and K. Keutzer, ``A Partial-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits'', Proceedings of the Int'l Test Conference, pages 403-410, Nashville, October 1991.

  57. Devadas, S., K. Keutzer and S. Malik, ``Delay Computation in Combinational Logic Circuits: Theory and Algorithms'', Proceedings of the Int'l Workshop on Logic Synthesis, Raleigh, May 1991 and Proceedings of the Int'l Conference on Computer-Aided Design, pages 176-179, Santa Clara, November 1991.

  58. Van Aelten, F., J. Allen and S. Devadas, ``Verification of Relations Between Synchronous Machines'', Proceedings of the Int'l Workshop on Logic Synthesis, Raleigh, May 1991 and Proceedings of the Int'l Conference on Computer-Aided Design, pages 380-383, Santa Clara, November 1991.

  59. Kukula, J., and S. Devadas, ``Finite State Machine Decomposition By Transition Pairing'', Proceedings of the Int'l Conference on Computer-Aided Design, pages 414-417, Santa Clara, November 1991.

  60. Devadas, S., K. Keutzer, S. Malik and A. Wang, ``Event Suppression: Improving the Efficiency of Timing Simulation for Synchronous Digital Circuits'', Proceedings of the Brown/MIT Conference on Advanced Research in VLSI and Parallel Systems, pages 195-209, Providence, March 1992.

  61. Van Aelten, F., J. Allen and S. Devadas, ``Compositional Verification of Systems with Synchronous Globally Timed Control'', Proceedings of the Brown/MIT Conference on Advanced Research in VLSI and Parallel Systems, pages 281-296, Providence, March 1992.

  62. Van Aelten, F., S. Devadas and A. Ghosh, ``Test Generation and Verification Across Differing Levels of Abstraction'', Proceedings of the 3rd Synthesis and Simulation Meeting and International Exchange (SASIMI) Workshop, pages 211-222, Kobe, April 1992.

  63. Devadas, S., K. Keutzer, S. Malik and A. Wang, ``Certified Timing Verification and the Transition Delay of a Circuit'', Proceedings of the 29th Design Automation Conference, Anaheim, pages 549-555, June 1992. Also in the Proceedings of Tau 92: 1992 ACM Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Princeton, March 1992.

  64. Ghosh, A., S. Devadas, K. Keutzer and J. White, ``Estimation of Average Switching Activity in Combinational and Sequential Circuits'', Proceedings of the 29th Design Automation Conference, Anaheim, pages 253-259, June 1992.

  65. Devadas, S., K. Keutzer, S. Malik and A. Wang, ``Computation of Floating Mode Delay in Combinational Logic Circuits: Practice and Implementation'', Proceedings of the International Symposium on Logic Synthesis and Microprocessor Architecture, pages 68-75, Kyushu, July 1992. Also in the Proceedings of Tau 92: 1992 ACM Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Princeton, March 1992.

  66. Devadas, S., H-F. Jyu, K. Keutzer and S. Malik, ``Statistical Timing Analysis of Combinational Logic Circuits'', Proceedings of the Int'l Conference on Computer Design: VLSI in Computers and Processors, Cambridge, pages 38-43, October 1992. Also in the Proceedings of Tau 92: 1992 ACM Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Princeton, March 1992.

  67. Van Aelten, F., S. Liao, J. Allen and S. Devadas, ``Automatic Generation and Verification of Sufficient Correctness Properties for Synchronous Processors'', Proceedings of the Int'l Conference on Computer-Aided Design, pages 183-187, Santa Clara, November 1992.

  68. Shen, A., A. Ghosh, S. Devadas and K. Keutzer, ``On Average Power Dissipation and Random Pattern Testability of Combinational Logic Circuits'', Proceedings of the Int'l Conference on Computer-Aided Design, pages 402-407, Santa Clara, November 1992.

  69. Devadas, S., K. Keutzer, S. Malik and A. Wang, ``Verification of Asynchronous Circuits with Bounded Wire Delays'', Proceedings of the Int'l Conference on Computer-Aided Design, pages 188-195, Santa Clara, November 1992.

  70. Camposano, R., S. Devadas, K. Keutzer, S. Malik and A. Wang, ``Implicit Enumeration Techniques Applied to Asynchronous Circuit Verification'', Proceedings of the 26th Hawaii International Conference on System Sciences, pages 300-309, Koloa, January 1993.

  71. Shen, A., S. Devadas, and A. Ghosh, ``Probabilistic Construction and Manipulation of Free Boolean Diagrams'', Proceedings of the Int'l Conference on Computer-Aided Design, pages 544-549, Santa Clara, November 1993.

  72. Liao, S., S. Devadas, and A. Ghosh, ``Boolean Factorization using Multiple-Valued Logic Minimization'', Proceedings of the Int'l Conference on Computer-Aided Design, pages 606-611, Santa Clara, November 1993.

  73. Monteiro, J., S. Devadas, and A. Ghosh, ``Retiming Sequential Circuits for Low Power'', Proceedings of the Int'l Conference on Computer-Aided Design, pages 398-402, Santa Clara, November 1993.

  74. Monteiro, J., J. Kukula, S. Devadas, and H. Neto, ``Bitwise Encoding of Finite State Machines'', Proceedings of the 7th Int'l Conference on VLSI Design, Calcutta, pages 379-382, January 1994.

  75. Bhagwati, V. and S. Devadas, ``Automatic Verification of Pipelined Microprocessors'', Proceedings of the 31st Design Automation Conference, San Diego, pages 603-608, June 1994.

  76. Monteiro, J., S. Devadas and B. Lin, ``A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits'', Proceedings of the 31st Design Automation Conference, San Diego, pages 12-17, June 1994.

  77. Lin, B., and S. Devadas, ``Synthesis of Hazard-Free Multilevel Logic Under Multiple-Input Changes from Binary Decision Diagrams'', Proceedings of the Int'l Conference on Computer-Aided Design, San Jose, pages 542-549, November 1994.

  78. Alidina, M., J. Monteiro, S. Devadas, A. Ghosh and M. Papaefthymiou, ``Precomputation-Based Sequential Logic Optimization for Low Power'', Proceedings of the Int'l Conference on Computer-Aided Design, San Jose, pages 74-81, November 1994.

  79. Yun, K., B. Lin, D. Dill and S. Devadas, ``Performance-Driven Synthesis of Asynchronous Controllers'', Proceedings of the Int'l Conference on Computer-Aided Design, San Jose, pages 550-557, November 1994.

  80. Monteiro, J., J. Rinderknecht, S. Devadas and A. Ghosh, ``Optimization of Combinational and Sequential Logic Circuits for Low Power Using Precomputation'', Proceedings of the 1995 Chapel Hill Conference on Advanced Research in VLSI, Chapel Hill, pages 430-444, March 1995.

  81. Liao, S., S. Devadas and K. Keutzer, ``Code Density Optimization for Embedded DSP Processors Using Data Compression Techniques'', Proceedings of the 1995 Chapel Hill Conference on Advanced Research in VLSI, Chapel Hill, pages 272-285, March 1995.

  82. Monteiro J., and S. Devadas, ``Techniques for the Power Estimation of Sequential Logic Circuits Under User-Specified Input Sequences and Programs'', Proceedings of the International Symposium on Low Power Design, Dana Point, pages 33-38, April 1995.

  83. Liao, S., S. Devadas, K. Keutzer, S. Tjiang and A. Wang, ``Code Optimization Techniques in Embedded DSP Microprocessors'', Proceedings of the 32nd Design Automation Conference, San Francisco, pages 599-604, June 1995.

  84. Devadas, S. and S. Malik, ``A Survey of Optimization Techniques Targeting Low Power VLSI Circuits'', Proceedings of the 32nd Design Automation Conference, San Francisco, pages 242-247, June 1995.

  85. Liao, S., S. Devadas, K. Keutzer, S. Tjiang and A. Wang, ``Storage Assignment to Decrease Code Size'', Proceedings of the SIGPLAN Programming Language Design and Implementation Symposium, San Diego, pages 186-195, June 1995.

  86. Liao, S., S. Devadas, K. Keutzer and S. Tjiang, ``Instruction Selection and Scheduling Using Binate Covering For Code Size Optimization'', Proceedings of the Int'l Conference on Computer-Aided Design, San Jose, pages 393-399, November 1995.

  87. Lam, K. and S. Devadas, ``PECS: A Peak Current and Power Simulator for CMOS Combinational Circuits'', Proceedings of IEEE International Symposium on Circuits and Systems, Volume 4, pages 488-491, Atlanta, May 1996.

  88. Monteiro, J., S. Devadas, P. Ashar, and A. Mauskar, ``Scheduling Techniques to Enable Power Management'', Proceedings of the 33rd Design Automation Conference, pages 349-352, Las Vegas, June 1996.

  89. Devadas, S., A. Ghosh and K. Keutzer, ``An Observability-Based Code Coverage Metric for Functional Simulation'', Proceedings of the Int'l Conference on Computer-Aided Design, pages 418-425, San Jose, November 1996.

  90. Hadjiyiannis, G., A. P. Chandrakasan and S. Devadas, ``A Low-Power, Low-Bandwidth Protocol for Remote Wireless Terminals'', Proceedings of the IEEE Global Telecommunications Conference, pages 22-28, London, November 1996.

  91. Sudarsanam, A., S. Liao and S. Devadas, ``Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Processors and ASIPs'', Proceedings of the 34th Design Automation Conference, Anaheim, pages 287-292, June 1997.

  92. Hadjiyiannis, G., S. Hanono and S. Devadas, ``ISDL: An Instruction Set Description Language for Retargetability'', Proceedings of the 34th Design Automation Conference, Anaheim, pages 299-302, June 1997.

  93. Liao, S., and S. Devadas, ``Solving Covering Problems Using LPR-Based Lower Bounds'', Proceedings of the 34th Design Automation Conference, Anaheim, pages 117-120, June 1997.

  94. Costa, J. C., J. Monteiro, and S. Devadas, ``Switching Activity Estimation Using Limited Depth Reconvergent Path Analysis'', Proceedings of the Int'l Symposium on Low Power Electronic Design, Monterey, pages 184-189, August 1997.

  95. Hanono, S., and S. Devadas, ``Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator'', Proceedings of the 35th Design Automation Conference, San Francisco, pages 510-515, June 1998.

  96. Fallah, F., S. Devadas, and K. Keutzer, ``Functional Test Generation Using Linear Programming and 3-Satisfiability'', Proceedings of the 35th Design Automation Conference, San Francisco, pages 528-533, June 1998.

  97. Fallah, F., S. Devadas, and K. Keutzer, ``OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Simulation'', Proceedings of the 35th Design Automation Conference, San Francisco, pages 152-157, June 1998.

  98. S. Devadas, and K. Keutzer, ``An Algorithmic Approach to Optimizing Fault Coverage for BIST Logic Synthesis'', Proceedings of the International Test Conference, pages 164-172, October 1998.

  99. Fallah, F., S. Devadas, and P. Ashar, ``Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage'', Proceedings of the 36th Design Automation Conference, New Orleans, pages 666-671, June 1999.

  100. Hadjiyiannis, G., P. Russo, and S. Devadas, ``A Methodology for Accurate Performance Evaluation in Architecture Exploration'', Proceedings of the 36th Design Automation Conference, New Orleans, pages 927-932, June 1999.

  101. Hadjiyiannis, G., P. Russo, and S. Devadas, ``Automatic Architecture Evaluation for Hardware/Software Codesign'', Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, pages 47-53, September 1999.

  102. Costa, J., Monteiro, L. M. Silveira, and S. Devadas, ``A Probabilistic Approach to RT-Level Power Modeling'', Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, pages 911-914, September 1999.

  103. Chatterjee, S., and S. Devadas, ``The MASC Composable Computing Infrastructure for Intelligent Environments'', Proceedings of the 25th Annual Conference of the IEEE Industrial Electronics Society (IECON 99), December 1999.

  104. Chiou, D., P. Jain, L. Rudolph, and S. Devadas, ``Application-Specific Memory Management for Embedded Systems Using Software-Controlled Caches'', Proceedings of the 37th Design Automation Conference, pages 416-419, June 2000.

  105. Fallah, F., and S. Devadas, ``Functional Vector Generation from HDL Models for an Observability-Based Code Coverage Metric'', SCI2000 and ISAS2000, Volume VIII Computer Science and Engineering: part II, pages 725-730, July 2000.

  106. Engels, D. W., and S. Devadas, ``A New Approach to Solving the Hardware-Software Partitioning Problem in Embedded System Design'', Proceedings SBCCI 2000, 13th Symposium on Integrated Circuits and Systems Design, pages 275-280, September 2000.

  107. Costa, J., S. Devadas, and J. Monteiro, ``Observability Analysis of Embedded Software for Coverage-Directed Validation'', Proceedings of the Int'l Conference on Computer-Aided Design, pages 27-32, November 2000.

  108. Suh, G. E., S. Devadas, and L. Rudolph, ``Analytical Cache Models with Application to Cache Partitioning'', Proceedings of the 15th International Conference on Supercomputing, pages 1-12, June 2001.

  109. Suh, G. E., L. Rudolph, and S. Devadas, ``Effects of Memory Performance on Parallel Job Scheduling'', Lecture Notes in Computer Science 2221, Proceedings of the Job Scheduling Workshop, pages 116-132, July 2001.

  110. Suh, G. E., L. Rudolph, and S. Devadas, ``Dynamic Cache Partitioning for Simultaneous Multithreading Systems'', Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS2001), pages 635-641, August 2001.

  111. Jain, P., S. Devadas, D. Engels, and L. Rudolph, ``Software-Assisted Cache Replacement Mechanisms for Embedded Systems'', Proceedings of the Int'l Conference on Computer-Aided Design, pages 119-126, November 2001.

  112. Suh, G. E., S. Devadas, and L. Rudolph, ``A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning'', Proceedings of the 8th International Symposium on High Performance Computer Architecture (HPCA'02), pages 117-128, February 2002.

  113. Burnside, M., D. Clarke, A. Maywah, T. Mills, S. Devadas, and R. Rivest, ``Proxy-Based Security Protocols in Networked Mobile Devices'', Proceedings of the 17th ACM Symposium on Applied Computing (Security Track), pages 265-272, March 2002.

  114. Clarke, D., B. Gassend, T. Kotwal, M. Burnside, M. van Dijk, S. Devadas, and R. Rivest, ``The Untrusted Computer Problem and Camera-Based Authentication'', Lecture Notes in Computer Science 2414, Proceedings of the International Conference on Pervasive Computing (Pervasive2002), pages 114-124, August 2002.

  115. Gassend, B., D. Clarke, M. van Dijk, and S. Devadas, ``Silicon Physical Random Functions'', Proceedings of the Computer and Communication Security Conference, November 2002.

  116. Gassend, B., D. Clarke, M. van Dijk and S. Devadas, ``Controlled Physical Random Functions'', Proceedings of the 18th Annual Computer Security Applications Conference, December 2002.

  117. Gassend, B., G. E. Suh, D. Clarke, M. van Dijk and S. Devadas, ``Caches and Merkle Trees for Efficient Memory Authentication'', Proceedings of the 9th International Symposium on High Performance Computer Architecture (HPCA'03), February 2003.

  118. Gassend, B., D. Clarke, M. van Dijk and S. Devadas, ``Delay-Based Authentication of Integrated Circuits'', Proceedings of the 18th ACM Symposium on Applied Computing (Security Track), March 2003.

  119. Raman, S., D. Clarke, M. Burnside, S. Devadas and R. Rivest, ``Access-Controlled Resource Discovery for Pervasive Networks'', Proceedings of the 18th ACM Symposium on Applied Computing (Security Track), March 2003.

  120. Jain, P., E. G. Suh, and S. Devadas, ``Intelligent SRAM (ISRAM) for Improved Embedded System Performance'', Proceedings of the 40th Design Automation Conference, June 2003.

  121. Suh, E. G., D. Clarke, B. Gassend, M. van Dijk and S. Devadas, ``AEGIS: Architectures for Tamper-Evident and Tamper-Resistant Processing'', Proceedings of the 17th Int'l Conference on Supercomputing, June 2003.

4. Other Major Publications:

  1. Devadas, S., H-K. T. Ma and A Sangiovanni-Vincentelli, ``Logic Verification, Testing and their Relationship to Logic Synthesis'', in Testing and Diagnosis of VLSI and ULSI, pages 181-245, Nijhoff, 1988.

  2. Devadas, S., ``Techniques for Optimization-Based Synthesis of Digital Systems'', Electronics Research Laboratory Memorandum M88/54, University of California, Berkeley, August 1988.

  3. Devadas, S., K. Keutzer, A. R Newton, ``New Trends in Testing and Verification'', Int'l Conference on Computer-Aided Design Tutorial, Santa Clara, November 1989.

  4. Brayton, R., S. Devadas, K. Keutzer and R. Rudell, ``Synthesis of Sequential Circuits'', 27th Design Automation Conference Tutorial, Orlando, June 1990.

  5. Devadas, S., and K. Keutzer, ``Synthesis for Testability'', Int'l Conference on Computer-Aided Design Tutorial, Santa Clara, November 1990.

  6. Araujo, G., S. Devadas, K. Keutzer, S Liao, S. Malik, A. Sudarsanam, S. Tjiang and A Wang, ``Challenges in Code Generation for Embedded Processors'', in Code Generation for Embedded Processors, pages 48-64, Kluwer Academic Publishers, 1995.

  7. Chandrakasan, A. P., S. Devadas and S. Malik, ``Optimization Techniques for Low Power VLSI Circuits'', Int'l Conference on Computer-Aided Design Tutorial, Santa Clara, November 1995.

  8. Liao, S., S. Devadas, K. Keutzer, S. Tjiang, A. Wang, G. Araujo, A. Sudarsanam, S. Malik, V. Zivojnovic, and H. Meyr., ``Code Generation and Optimization Techniques for Embedded Digital Signal Processors.'' in G. De Micheli and M. Sami, editors, Hardware-Software Co-Design, ch. 7, pages 165-186. Kluwer Academic Publishers, 1996.

  9. Silveira, L. M., S. Devadas and R. Reis, Editors, ``VLSI: Systems on a Chip'', Proceedings of the IFIP TC10 WG10.5 Tenth International Conference on Very Large Scale Integration (VLSI'99), Kluwer Academic Publishers, 1999.

  10. Gassend, B., D. Clarke, M. van Dijk and S. Devadas, ``Silicon Physical Unknown Functions and Secure Smartcards'', Laboratory for Computer Science Technical Report 833, May 2002.

  11. Gassend, B., D. Clarke, M. van Dijk and S. Devadas, ``Protocols and Applications of Controlled Silicon Physical Unknown Functions'', Laboratory for Computer Science Technical Report 845, June 2002.

  12. Gassend, B., D. Clarke, M. van Dijk and S. Devadas, ``Delay-Based Circuit Authentication with Application to Key Cards'', Laboratory for Computer Science Technical Report 854, June 2002.

  13. Gassend, B., E. Suh, D. Clarke, M. van Dijk and S. Devadas, ``Caches and Merkle Trees for Efficient Memory Authentication'', Laboratory for Computer Science Technical Report 857, July 2002.

  14. Clarke, D., B. Gassend, B., E. Suh, M. van Dijk and S. Devadas, ``Offline Authentication of Untrusted Storage'', Laboratory for Computer Science Technical Memorandum 631, August 2002.

  15. Clarke, D., B. Gassend, B., E. Suh, M. van Dijk and S. Devadas, ``Offline Integrity Checking of Untrusted Storage'', Laboratory for Computer Science Technical Report 871, November 2002.

  16. Suh, E. G., D. Clarke, B. Gassend, M. van Dijk and S. Devadas, ``Hardware Mechanisms for Memory Integrity Checking'', Laboratory for Computer Science Technical Report 872, November 2002.

  17. Suh, E. G., D. Clarke, B. Gassend, M. van Dijk and S. Devadas, ``AEGIS: Architecture for Tamper-Evident and Tamper-Resistant Processing'', Laboratory for Computer Science Technical Report 883, February 2003.

5. Invited Talks, Panel Discussions and Tutorials:

  1. ``Module Generation in the Berkeley Synthesis Environment'', Digital Equipment Corporation, Hudson, Massachusetts, August 1986.

  2. ``Topological Optimization of Multiple-Level Array Logic'', AT&T Bell Laboratories, Murray Hill, New Jersey, December 1986.

  3. ``Sequential Test Generation'', Hewlett-Packard Laboratories, Palo Alto, June 1988.

  4. ``Synthesis Procedures for Fully and Easily Testable Sequential Machines'', AT&T Bell Laboratories, Murray Hill, New Jersey, January 1989.

  5. ``Exact Algorithms for State Assignment'', AT&T Bell Laboratories, Murray Hill, New Jersey, June 1989.

  6. ``Sequential Test Generation and Synthesis for Testability'', National Science Foundation, Washington D. C., June 1989.

  7. Panel Discussion on ``Synthesis for Testability'', Int'l Conference on Computer Design: VLSI in Computers, Cambridge, October 1989.

  8. ``Synthesis for Testability'' DARPA Microsystems and Prototyping Semi-Annual Meeting, Washington D.C., November 1989.

  9. Roundtable Discussion on ``Synthesis for Testability'', Santa Clara, November 1989 (transcript appeared in the December 1990 issue of IEEE Design and Test Magazine).

  10. Tutorial on ``New Trends in Testing and Verification'', Int'l Conference on Computer-Aided Design, Santa Clara, November 1989.

  11. ``Logic Synthesis and Testing Research at MIT'', Princeton University, Princeton, November 1989.

  12. ``Synthesis for Combinational and Sequential Logic Testability'', University of Colorado, Boulder, Boulder, January 1990.

  13. Panel Discussion on ``System-Level Verification: Can We Make it Formal?'', IEEE VLSI Workshop, Tampa, February 1990.

  14. Panel Discussion on ``New Trends in Testing and Verification'', Int'l Conference on Circuits and Systems, New Orleans, May 1990.

  15. Panel Discussion on ``Testing Strategies for the 1990's'', 27th Design Automation Conference, Orlando, June 1990.

  16. Tutorial on ``Synthesis of Sequential Circuits'', 27th Design Automation Conference, Orlando, June 1990.

  17. ``Synthesis of Delay-Fault Testable Integrated Circuit Designs'', DARPA Microsystems and Prototyping Semi-Annual Meeting, Chapel Hill, October 1990.

  18. Tutorial on ``Synthesis for Testability'', Int'l Conference on Computer-Aided Design, Santa Clara, November 1990.

  19. ``Sequential Logic Synthesis and Synthesis for Testability'', Cadence Inc., San Jose, November 1991.

  20. ``Combinational and Sequential Logic Verification Using General Binary Decision Diagrams'', IBM T. J. Watson Research Center, Yorktown Heights, February 1991.

  21. ``Formal Verification'', Berkeley/Boulder/Stanford Workshop on Logic Synthesis, Monterey, April 1991.

  22. ``Formal Verification'', University of Iowa EE Graduate Colloquium, Iowa City, April 1991.

  23. Panel Discussion on ``Intellectual Property'', 28th Design Automation Conference, San Francisco, June 1991.

  24. ``Verification of Behavioral Specifications Against Synthesized Logic-Level Implementations'', IFIP WG 10.5 Int'l Workshop on the Relationships Between Synthesis, Test and Verification, Berkeley, November 1991.

  25. ``Delay Computation in Combinational Logic Circuits'', C & C Research Laboratories, NECUSA, Princeton, February 1992.

  26. ``Verification at the Behavioral Level'', Synthesis and Simulation Meeting and Int'l Exchange Workshop, Kobe, Japan, April 1992.

  27. Panel Discussion on ``Engineering Skills in the Year 2000: What Are They?'', Custom Integrated Circuits Conference, Boston, May 1992.

  28. ``Automatic Procedures for the Behavioral Verification of VLSI Circuits'', University of Massachusetts at Amherst, Amherst, May 1992.

  29. ``Formal Methods for Behavioral Verification'', Mitsubishi Electronics Research Laboratory, Sunnyvale, June 1992.

  30. ``Synthesis for Testability and Low Power'', DARPA Joint Microsystems and Computer Systems PI Meeting, Daytona Beach, September 1992.

  31. ``Probabilistic Manipulation of Boolean Functions'', DARPA Joint Microsystems and Computer Systems PI Meeting, Arlington, April 1993.

  32. ``Introduction to Digital Signal Processing Algorithms'', Synopsys Summer Workshop on Embedded Systems, Mountain View, August 1993.

  33. ``Computer-Aided Design and Verification Strategies for Real-Time Embedded Systems'', Workshop on Real-Time Control, Harvard University, Cambridge, April 1994.

  34. Panel Discussion on ``Low Power Design Techniques: Is CAD the Solution?'', Int'l Workshop on Low Power Design, Napa Valley, April 1994.

  35. ``Synthesis for Testability'', MIT EECS Colloquium, October 1994.

  36. ``Code Generation and Optimization in Embedded Systems'', DARPA Joint Microsystems and Computer Systems PI Meeting, Phoenix, April 1995.

  37. ``A Survey of Optimization Techniques Targeting Low Power VLSI Circuits'', 32nd Design Automation Conference, San Francisco, June 1995.

  38. ``Code Generation and Optimization for Embedded DSP Processors'', C & C Research Laboratories, NECUSA, Princeton, September 1995.

  39. Tutorial on ``Optimization Techniques for Low Power VLSI Circuits'', Int'l Conference on Computer-Aided Design, Santa Clara, November 1995.

  40. ``Retargetable Code Generation in Embedded Systems'', DARPA Joint Microsystems and Computer Systems PI Meeting, San Diego, June 1996.

  41. ``Why CAD for VLSI -> Software Compilation'', CANDE Workshop, Banff, Alberta, Canada, April 1997.

  42. ``Application-Specific Processor Design Using a Retargetable Compiler and Simulator'', IBM, Yorktown Heights, New York, December 1997.

  43. ``Intelligent Environments: Offloading Human Work on Computers'', LCS Annual Meeting, Cape Cod, MA, June 1998.

  44. ``A Design Environment for Application-Specific Programmable Processors'', Frontiers in System Design Colloquium, Synopsys, Mountain View, CA, July 1998.

  45. ``A Design Environment for Application-Specific Programmable Processors'', Tensilica, Cupertino, CA, July 1998.

  46. Tutorial on ``CAD Techniques for Embedded System Design'', 12th Int'l Conference on VLSI Design, Goa, India, January 1999.

  47. ``A Framework for Automation Using Networked Information Appliances'', NTT, Atsugi, Japan, March 1999.

  48. ``Info Automation'', LCS 35th Anniversary, Cambridge, MA, April 1999.

  49. ``Information Automation'', Understanding the New World of Information-99, Taipei, May 1999.

  50. ``Malleable Caches'', Data-Intensive Systems Program DARPA Semi-Annual Meeting, Puerto Rico, October 1999.

  51. ``Impact of Emerging Application Domains on Architectures, Synthesis, Verification, and Test'', NSF Panel on Impact of Emerging Application Domains, National Science Foundation, Arlington, November 1999.

  52. ``Automation in Oxygen'', Oxygen Alliance Annual Meeting, Laboratory for Computer Science, MIT, June 2000.

  53. ``Devices, Automation and Security'', Oxygen Alliance Annual Meeting, Laboratory for Computer Science, MIT, June 2001.

  54. ``Multicentric Computing'', LCS Annual Meeting, Cape Cod, MA, June 2001.

  55. ``Secure Resource Discovery'', Oxygen Alliance Annual Meeting, Laboratory for Computer Science, MIT, June 2002.

  56. ``Physical Random Functions'', Princeton University, October 2002.

  57. ``Physical Random Functions and Secure Computing'', CSE Colloquium, Pennsylvania State University, October 2002.

  58. ``Physical Random Functions and Secure Computing'', HPQ Research Laboratories, Palo Alto, CA, March 2003.

  59. ``Tamper-Resistant Platforms for Secure Systems'', Joint C3S/CLACM Seminar, Carnegie-Mellon University, Pittsburgh, April 2003.

Theses Supervised by SRINIVAS DEVADAS

Summary:

  Total Completed In Progress
S.B. 3 3 0
AUP 1 1 1
S.M. 31 29 2
Meng 10 9 1
Doctoral      
As Supervisor: 14 9 5
As Reader: 13 10 3

Bachelor's Theses

Kevin Lam, ``Performance-Oriented Synthesis of Finite State Machines'', May 1989.

Stan Liao, ``Sequential Test Generation Using Binary Decision Diagrams'', May 1991.

Curtis Chen, ``An Analysis of Global Flow and Algebraic Factoring Techniques in Logic Synthesis'', May 1991.

AUP

Fumiaki Shiraishi, ``A Remote Control as an Information Appliance'', May 1999.

Master's Theses

Michael J. Bryan, ``Synthesis Procedures to Preserve Testability of Multilevel Combinational Logic Circuits'', May 1990.

Jennifer Hamel, ``A Tool for Verifying How Well a Guided Probe Tracks Faults'', (co-supervised with D. Wiles at GenRad), December 1990.

Paul Anderson, ``Characterization of a Configurable Read Only Memory Generator'', (co-supervised with K. Drozdowicz at Motorola), April 1991.

My CaoHuy, ``Optimization of Self-Test Design for BiCMOS SRAMs'', (co-supervised with D. Dreibelbis at IBM), May 1991.

Kevin Lam, ``Strategies for Peak Current Estimation in CMOS Logic Circuits'', August 1991.

Curtis Chen, ``Area Optimization of Single Output Functions'', August 1991.

Marina Frants, ``State-Grouping: A Pre-processing step for State Assignment Algorithms'', August 1991.

Amelia Shen, ``Performance Optimization of Large Sequential Circuits'', May 1992.

Stephen Peters, ``Algorithms for Testing Boundary-Scan Equipped Circuits'', (co-supervised with G. Robinson at GenRad) May 1992.

Brian Pan, ``Automated Partitioning of Digital Circuit Netlists Into Multiple Multichip Modules'', (co-supervised with J. Wong at Raytheon) June 1992.

Stan Liao, ``Automatic Generation and Verification of Sufficient Correctness Conditions for Array Processors'', August 1992.

Kelly Bai, ``Accelerating Model Checking in Event-Based Compositional Verification'', December 1992.

John C. Baker, Jr., ``A Hardware Approach for Resolver to Angle Converters'', (co-supervised with E. Cusson at Draper) August 1993.

Vishal Bhagwati, ``Automatic Verification of Pipelined Processors'', December 1993.

Christopher Niessen, ``A VLSI Systolic Array Processor for Complex Singular Value Decomposition'', (co-supervised with S. R. Broadstone at Lincoln) May 1994.

Mazhar Alidina, ``Precomputation-Based Sequential Logic Optimization for Low Power'', May 1994.

John Rinderknecht, ``A Power Reduction Algorithm for Combinational CMOS Circuits using Input Disabling'', January 1995.

Kendra Markle, ``A Methodology for Circuit Optimization'', (co-supervised with T. Fletcher of INTEL Corporation) January 1995.

Clara Sanchez, ``BIST Test Pattern Generator Based on Partitioning Circuit Inputs'', May 1995.

George Hadjiyiannis, ``A Protocol for Low-Power, Low-Bandwidth Remote Terminals'', (co-supervised with Prof. A. Chandrakasan at MIT) August 1995.

Farzan Fallah, ``A New Algorithm for Factorization of Logic Expressions'', January 1996.

Ya-Chieh Lai, ``Test and Diagnosis of Microprocessor Memory Arrays Using Functional Patterns'', May 1996.

Mark Sadowski, ``Design and Implementation of an Interactive Assembly Language Editor for the Parallel Processor of the TMS320C8x'', May 1996.

Yi-Hsiu E. Chen, ``The Virtual Tester'', February 1997.

Gookwon Edward Suh, ``Analytical Cache Models with Application to Cache Partitioning'', (cosupervised with Dr. Larry Rudolph at MIT), February 2001.

Todd Mills, ``Architcture and Implementation of Secure Device Communication in Oxygen'', May 2001.

Mohammed Ali Tariq, ``Architcture and Implementation of Automation and Scripting in Oxygen'', May 2001.

Thomas Kotwal, ``The Untrusted Computer Problem and Camera Based Authentication Using Optical Character Recognition'', May 2002.

Blaise Gassend, ``Physical Random Functions'', February 2003.

Engineer's Theses

Cheng Cheng, ``Building the MASC Information Appliance Prototype'', May 1999.

Pietro Russo, ``The Hgen Hardware Synthesis System'', May 1999.

Venkatesh Satish, ``An Expert System to Detect and Diagnose Failures in DRAM'', September 1999.

Mark L. Huang, ``Implementation of the MASC Information Appliance'', February 2000.

Eric Mui, ``Optimizing Memory Accesses for the Architecture Exploration System (ARIES)'', May 2000.

Joseph Adam Croswell, ``A Model for Analysis of the Effects of Redundancy and Error Correction on DRAM Memory Yield and Reliability'', September 2000.

Christine H. Tran, ``Incremental Switching Factor Calculation for Power Estimation'', May 2001.

Matthew Burnside, ``An Architecture for Secure Resource Discovery'', February 2002.

Sanjay Raman, ``A Secure Framework for Access-Controlled Resource Discovery in Dynamic Networks'', May 2002.

Doctoral Theses, Supervisor

Filip Van Aelten, ``Automatic Procedures for the Behavioral Verification of VLSI Circuits'', May 1992.

Amelia Shen, ``Probabilistic Representation and Manipulation of Boolean Functions Using Free Boolean Diagrams'', July 1994.

Stan Liao, ``Code Generation and Optimization for Embedded Digital Signal Processors'', December 1995.

José Monteiro, ``A Computer-Aided Design Methodology for Low Power Sequential Logic Circuits'', May 1996.

Farzan Fallah, ``Coverage-Directed Validation of Hardware Models'', April 1999.

Silvina Hanono, ``Aviv: A Retargetable Code Generator for Embedded Processors'', May 1999.

George Hadjiyiannis, ``An Architecture Synthesis System for Embedded Processors'', May 2000.

Daniel Engels, ``Scheduling for Hardware-Software Partitioning in Embedded System Design'', May 2000.

Sandeep Chatterjee, ``"Composable System Resources as an Architecture for Networked Systems'', March 2001.

Prabhat Jain, ``Application-Specific Adaptive Memory Management'', December 2003 (expected).

Edward Suh, ``Architectures for Tamper-Evident and Tamper-Resistant Processing'', May 2005 (expected).

Doctoral Theses, Reader

Pranav Ashar, ``Synthesis of Sequential Circuits for VLSI Design'', (co-supervised with Prof. Richard Newton) University of California, Berkeley, August 1991.

Abhijit Ghosh, ``Techniques for Test Generation and Verification of VLSI Sequential Circuits'', (co-supervised with Prof. Richard Newton) University of California, Berkeley, August 1991.

Alexander Ishii, ``Timing in Level-Clocked Circuits'', December 1991.

Robert Armstrong, ``A Formal Approach to Incremental Consistency Maintenance in Multirepresentation VLSI Databases'', December 1991.

Marios Papaefthymiou, ``Timing Optimization of Level-Clocked Circuits'', August 1993.

Donald Baltus, ``Algorithmic Approaches to the Synthesis of Structured VLSI Systems'', December 1993.

Guido Araujo, ``Code Generation Algorithms for Digital Signal Processors '', Princeton University, May 1997.

Ashok Sudarsanam, ``Code Optimization Libraries for Retargetable Compilation for Embedded Digital Signal Processors '', Princeton University, May 1998.

Russ Tessier, ``Fast Place and Route Approaches for FPGAs'', September 1998.

Derek Chiou, ``Extending the Reach of Microprocessors Using Column and Curious Caching'', August 1999.

James Hoe, ``Operation-Centric Hardware Description and Synthesis'', August 2000.



Srini Devadas 05-22-2003