Design for Low Power

J. Monteiro, S. Devadas, A. Ghosh, K. Keutzer, and J. K. White, "Estimation of Average Switching Activity in Combinational Logic Circuits Using Symbolic Simulation", IEEE Transactions on CAD, Volume 16, Number 1, pages 121-127, January 1997.

M. Alidina, J. Monteiro, S. Devadas, A. Ghosh, and M. Papaefthymiou, "Precomputation-Based Sequential Logic Optimization for Low Power", IEEE Transactions on VLSI Systems, pp. 426-436, December 1994.

C-Y. Tsui, J. Monteiro, M. Pedram, S. Devadas, A. Despain, and B. Lin, "Power Estimation Methods for Sequential Logic Circuits", IEEE Transactions on VLSI Systems, pp. 404-416, September 1995. Best Paper Award.

G. Hadijiyiannis, A. Chandrakasan, and S. Devadas, "A Low Power, Low Bandwidth Protocol for Remote Wireless Terminals", MIT Technical Report, February 1996.

J. Monteiro, S. Devadas, P. Ashar, and A. Mauskar, "Scheduling Techniques to Enable Power Management", Proceedings of the 33rd Design Automation Conference, June 1996.

J. Costa, J. Monteiro, and S. Devadas, "Switching Activity Estimation Using Limited Depth Reconvergent Path Analysis ", Proceedings of the International Symposium on Low Power Electronic Design , April 1997.