;;; Trivial SimSynch FIFO design example.
;;; Copyright (C) 2003 Aubrey Jaffer

;;; This program is free software; you can redistribute it and/or modify
;;; it under the terms of the GNU General Public License as published by
;;; the Free Software Foundation; either version 2 of the License, or
;;; (at your option) any later version.
;;;
;;; This program is distributed in the hope that it will be useful,
;;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;;; GNU General Public License for more details.
;;;
;;; You should have received a copy of the GNU General Public License
;;; along with this program; if not, write to the Free Software
;;; Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111, USA.

(require 'simsynch)
(require 'models)
(require 'logic)
(require 'run)

(Time-stamp: "2003-06-22 18:29:28 jaffer")
(Revision-stamp: 1)			;Version number of firmware
(Company-stamp: "Voluntocracy")

;;(provide 'lift-bus)			;lift bidirectional signals to top.

#;FIFO Design.
(synch:register-ptag 'FIFO "ORCA" time-stamp:revision)

#;Simsynch synthesizable FIFO.
(synch:register-block 'FIFO 'wr-clk 'reset 60e6)

#;Clock to FIFO
(synch:definput FIFO:wr-clk wr-clk #f)
#;Clock to FIFO
(synch:definput FIFO:rd-clk rd-clk #f)

(defvar reset #f)			; don't move this
#;Asynchronous reset to FIFO.
(synch:definput FIFO:reset reset #f)

(define test-sequence '#(15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 6 9))
#;Input register for FIFO.
(synch:definput FIFO: din[7:0]
		(if (< 4 synch:count (+ 4 15))
		    (vector-ref test-sequence (+ -5 synch:count))
		    *xxxx*))

#;Write byte to FIFO.
(synch:definput FIFO: wr-en (< 4 synch:count (+ 4 9)))

#;Read BYTE from FIFO.
(synch:definput FIFO: rd-en (< 24 synch:count (+ 24 9)))

#;Length of FIFO.
(defconst fifolen 8)
(synch:fifo FIFO:fifo-8[7:0] #.fifolen
	    din[7:0] wr-en rd-en
	    FIFO:frst[7:0] #f #f #f)

#;FIFO fullness synchronized to wr-clk.
(synch:define FIFO: wr-count[3:0] 0 wr-count[3:0] #t
	      (- (+ wr-count[3:0] (if wr-en 1 0)) (if rd-en 1 0)))

#;FIFO output-data pipe.
(synch:define FIFO: dout[7:0] 0 dout[7:0] #t
	      (if rd-en frst[7:0] dout[7:0]))

#;FIFO is empty
(synch:define FIFO: empty #t empty #t (= 0 (synch:pre wr-count[3:0])))
#;FIFO is full
(synch:define FIFO: full #f full #t (= fifolen (synch:pre wr-count[3:0])))

(define-synchronous-system fifo

;;;================================================================
;;;			    Trace output.
;;;================================================================

  (dump:vhdl
   "fifo8-spew.dat"
   'fifo
   33e6
   wr-clk
   reset
;;; Dumps a text file with time series of the following signals
;;; providing stimulus and checks for Modelsim VHDL simulation.
   wr-en
   rd-en
   din[7:0]
   wr-count[3:0]
   empty
   full
   dout[7:0])

;;; This displays a (vertical) timing diagram on the console.
;;; Time increases downwards.
  (synch:print
   "cycle" synch:count
   reset
   "din" din[7:0]
   wr-en
   rd-en
   "dout" dout[7:0]
   "wr-cnt" wr-count[3:0]
   empty
   full
   )
  )
;;; All blocks have been entered into database.
(solidify-database *board*)

;;; So the timing diagram is displayed.
(set! print-timing #t)

;;; One cycle with reset = #t.
(fifo-sim 1)
(set! reset #f)

;;; Run simulation
(fifo-sim 40)

;;; cleanup
(if dump:port (force-output dump:port))

;;; Translate design to VHDL.
(require 'vhdl)
(translate-design *design*)