SIMSYNCH can translate its register-transfer-level designs to
MACHXL, Verilog, or VHDL formats. The bulk of the
work is performed by the files scm2mach, scm2vrlg, and
scm2vhdl. The file run.scm defines translate,
which drives the conversion.
The symbol design should correspond to a file named design.scm, which contains the definitions.
The symbol target-language can be:
machxl- MACHXL 2 is a format devised by AMD for their PLDs. MACHXL 3, 4, and 5 are an unrelated commercial product. MACHXL 2 was available for free at one time.
translatecreates a file named design.pds with the MACHXL definitions.verilog- Verilog is a popular High level Design Language. Translate creates a file named design.v with the Verilog definitions; and design.acf with pin-name assignments. The acf format is used by the Altera MAXPLUS2 Version 8 fitter. ACF is not yet supported.
vhdl- VHDL is a popular High level Design Language. Translate creates files named design-tag.vhd with the VHDL definitions.
SIMSYNCH translates the following functions:
SIMSYNCH translates the following syntaxes. Remember that you are limited to this set only for signals which will be translated for the benefit of a logic compiler.
andand.
ornumber-ornumber-or for combining clauses which return only vectorized
values or #f.
if(if <test> <consequent> <alternate>).
caseqaseqase is an extension of standard Scheme case: Each
clause of a case statement must begin with a list of literal
datums, the corresponding list in a qase statement may
contain either literal datums or the names of symbolic constants
preceded by a comma. A qase statement is equivalent to a
case statement in which all symbolic constants preceded by commas
have been replaced by the values of the constants. This use of comma,
(or, equivalently, unquote) is similar to that of
quasiquote except that the unquoted expressions must be
symbolic constants.
defconstdefconst, their values are
substituted in the head of each qase clause during macro
expansion. In practice defconst constants should be defined
before use.
synch:fifosynch:pre