--FILE      test_fifo.vhd
--ENTITY    fifo
--PROJECT   ??
--REVISION  1
--COMPANY   Voluntocracy
--AUTHOR    jaffer
--DATE      Sun Jun 22 19:29:28 2003

--PROCESS   ORCA


LIBRARY ieee;

USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

USE work.logical.all;
--
-- The (SIMSYNCH) file "logical.vhd" provides several utility functions
-- which may be used in this file:
--
-- FIF(test, consequent, alternate) is Functional-IF,
--	useful in contexts where VHDL disallows IF statements.
--
--	If TEST is True or '1', then return CONSEQUENT;
--	otherwise return ALTERNATE.
--
-- LOGBIT_P(index, operand)
--	returns True or '1' if OPERAND(INDEX) is '1';
--	otherwise returns False or '0'.
--
-- BIT_FIELD(operand, istart, iend)
--	returns OPERAND(IEND downto ISTART).
--
-- RSHIFT(operand, icnt)
--	shifts (unsigned) OPERAND ICNT bits to the right;
--	The low-order bits are truncated.
-- LSHIFT(operand, icnt)
--	shifts OPERAND ICNT bits to the left;
--	The low-order bits are padded with '0'.
--

--FIFO Design.

ENTITY fifo IS PORT (
   --Write byte to FIFO.
   wr_en: IN std_logic;
   --Clock to FIFO
   wr_clk: IN std_logic;
   --Asynchronous reset to FIFO.
   reset: IN std_logic;
   --Read BYTE from FIFO.
   rd_en: IN std_logic;
   --Clock to FIFO
   rd_clk: IN std_logic;
   --Input register for FIFO.
   din: IN std_logic_vector(7 DOWNTO 0);
   --FIFO fullness synchronized to wr-clk.
   wr_count: BUFFER std_logic_vector(3 DOWNTO 0);
   --FIFO is full
   full: BUFFER std_logic;
   --FIFO is empty
   empty: BUFFER std_logic;
   --FIFO output-data pipe.
   dout: BUFFER std_logic_vector(7 DOWNTO 0));
END fifo;

ARCHITECTURE model OF fifo IS
   --Clock to Output times for registers in this block
   CONSTANT  tCQ: TIME := 2.00000 ns;

   --Length of FIFO.
   CONSTANT fifolen: integer := 08;


--Registers

       SUBTYPE memory_bus_101 IS bit_vector (7 DOWNTO 0);
       TYPE memory_type_101 IS ARRAY (00 TO 08 - 01) OF memory_bus_101;

   --RAM implementing the FIFO.
   SIGNAL fifo_8: memory_type_101;


   --(circular) pointer to word to write.
   SIGNAL fifo_8_outidx:  std_logic_vector(3 DOWNTO 0);

   --(circular) pointer to word to read.
   SIGNAL fifo_8_inidx:  std_logic_vector(3 DOWNTO 0);

--Combinatorials

   --First-out word.
   SIGNAL frst:  std_logic_vector(7 DOWNTO 0);

   --Number of words in use.
   SIGNAL fifo_8_fullness:  std_logic_vector(3 DOWNTO 0);

BEGIN

 --RAM implementing the FIFO.
 PROCESS (wr_clk)
 BEGIN
   IF wr_clk'EVENT AND ('1' = wr_clk) THEN
     IF ('1' = wr_en) THEN
       fifo_8(Conv_Integer((07 AND fifo_8_inidx(3 DOWNTO 0)))) <= To_BitVector(din(7 DOWNTO 0)) AFTER tCQ;
     END IF;
   END IF;
 END PROCESS;

 --(circular) pointer to word to write.
 PROCESS (wr_clk, reset)
 BEGIN
   IF ('1' = reset) THEN
     fifo_8_outidx(3 DOWNTO 0) <= "0000" AFTER tCQ;
   ELSIF wr_clk'EVENT AND ('1' = wr_clk) THEN
     IF ('1' = rd_en) THEN
       fifo_8_outidx(3 DOWNTO 0) <= Conv_Std_Logic_Vector(01 + fifo_8_outidx(3 DOWNTO 0), 4) AFTER tCQ;
     END IF;
   END IF;
 END PROCESS;

 --(circular) pointer to word to read.
 PROCESS (wr_clk, reset)
 BEGIN
   IF ('1' = reset) THEN
     fifo_8_inidx(3 DOWNTO 0) <= "0000" AFTER tCQ;
   ELSIF wr_clk'EVENT AND ('1' = wr_clk) THEN
     IF ('1' = wr_en) THEN
       fifo_8_inidx(3 DOWNTO 0) <= Conv_Std_Logic_Vector(01 + fifo_8_inidx(3 DOWNTO 0), 4) AFTER tCQ;
     END IF;
   END IF;
 END PROCESS;

 --Number of words in use.
 fifo_8_fullness(3 DOWNTO 0) <= Conv_Std_Logic_Vector(fifo_8_inidx(3 DOWNTO 0) - fifo_8_outidx(3 DOWNTO 0), 4) AFTER tCQ;

 --First-out word.
 frst(7 DOWNTO 0) <= To_StdLogicVector(fifo_8(Conv_Integer((07 AND fifo_8_outidx(3 DOWNTO 0))))) AFTER tCQ;

 --FIFO fullness synchronized to wr-clk.
 PROCESS (wr_clk, reset)
 BEGIN
   IF ('1' = reset) THEN
     wr_count(3 DOWNTO 0) <= "0000" AFTER tCQ;
   ELSIF wr_clk'EVENT AND ('1' = wr_clk) THEN
     wr_count(3 DOWNTO 0) <= Conv_Std_Logic_Vector((wr_count(3 DOWNTO 0) + (fif(('1' = wr_en), 01, 00)))
		  - (fif(('1' = rd_en), 01, 00)), 4) AFTER tCQ;
   END IF;
 END PROCESS;

 --FIFO output-data pipe.
 PROCESS (wr_clk, reset)
 BEGIN
   IF ('1' = reset) THEN
     dout(7 DOWNTO 0) <= "00000000" AFTER tCQ;
   ELSIF wr_clk'EVENT AND ('1' = wr_clk) THEN
     IF ('1' = rd_en) THEN
       dout(7 DOWNTO 0) <= frst(7 DOWNTO 0) AFTER tCQ;
     END IF;
   END IF;
 END PROCESS;

 --FIFO is empty
 PROCESS (wr_clk, reset)
 BEGIN
   IF ('1' = reset) THEN
     empty <= '1' AFTER tCQ;
   ELSIF wr_clk'EVENT AND ('1' = wr_clk) THEN
     empty <= To_StdLogic(00
	     = ((wr_count(3 DOWNTO 0) + (fif(('1' = wr_en), 01, 00))) - (fif(('1' = rd_en), 01, 00)))) AFTER tCQ;
   END IF;
 END PROCESS;

 --FIFO is full
 PROCESS (wr_clk, reset)
 BEGIN
   IF ('1' = reset) THEN
     full <= '0' AFTER tCQ;
   ELSIF wr_clk'EVENT AND ('1' = wr_clk) THEN
     full <= To_StdLogic(fifolen
	     = ((wr_count(3 DOWNTO 0) + (fif(('1' = wr_en), 01, 00))) - (fif(('1' = rd_en), 01, 00)))) AFTER tCQ;
   END IF;
 END PROCESS;

END model; -- fifo