--FILE      test_stim.vhd
--ENTITY    stim
--PROJECT   ??
--REVISION  1
--COMPANY   Voluntocracy
--AUTHOR    jaffer
--DATE      Sun Jun 22 19:29:28 2003



LIBRARY ieee;

USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

USE work.logical.all;
--
-- The (SIMSYNCH) file "logical.vhd" provides several utility functions
-- which may be used in this file:
--
-- FIF(test, consequent, alternate) is Functional-IF,
--	useful in contexts where VHDL disallows IF statements.
--
--	If TEST is True or '1', then return CONSEQUENT;
--	otherwise return ALTERNATE.
--
-- LOGBIT_P(index, operand)
--	returns True or '1' if OPERAND(INDEX) is '1';
--	otherwise returns False or '0'.
--
-- BIT_FIELD(operand, istart, iend)
--	returns OPERAND(IEND downto ISTART).
--
-- RSHIFT(operand, icnt)
--	shifts (unsigned) OPERAND ICNT bits to the right;
--	The low-order bits are truncated.
-- LSHIFT(operand, icnt)
--	shifts OPERAND ICNT bits to the left;
--	The low-order bits are padded with '0'.
--
USE std.textio.all;
USE work.readtext.all;
--
--"readtext.vhd" extends the std.textio function READ to std_ulogic_vector.
--
ENTITY tb IS END tb;

ARCHITECTURE stimulus OF tb IS

   --FIFO Design.
   COMPONENT fifo PORT(
      --Write byte to FIFO.
      wr_en: IN std_logic;
      --Clock to FIFO
      wr_clk: IN std_logic;
      --Asynchronous reset to FIFO.
      reset: IN std_logic;
      --Read BYTE from FIFO.
      rd_en: IN std_logic;
      --Clock to FIFO
      rd_clk: IN std_logic;
      --Input register for FIFO.
      din: IN std_logic_vector(7 DOWNTO 0);
      --FIFO fullness synchronized to wr-clk.
      wr_count: BUFFER std_logic_vector(3 DOWNTO 0);
      --FIFO is full
      full: BUFFER std_logic;
      --FIFO is empty
      empty: BUFFER std_logic;
      --FIFO output-data pipe.
      dout: BUFFER std_logic_vector(7 DOWNTO 0));
   END COMPONENT;


   --Write byte to FIFO.
   SIGNAL wr_en:  std_logic;

   --Clock to FIFO
   SIGNAL wr_clk:  std_logic;

   --Asynchronous reset to FIFO.
   SIGNAL reset:  std_logic;

   --Read BYTE from FIFO.
   SIGNAL rd_en:  std_logic;

   --Clock to FIFO
   SIGNAL rd_clk:  std_logic;

   --Input register for FIFO.
   SIGNAL din:  std_logic_vector(7 DOWNTO 0);

   --FIFO fullness synchronized to wr-clk.
   SIGNAL wr_count:  std_logic_vector(3 DOWNTO 0);

   --FIFO is full
   SIGNAL full:  std_logic;

   --FIFO is empty
   SIGNAL empty:  std_logic;

   --FIFO output-data pipe.
   SIGNAL dout:  std_logic_vector(7 DOWNTO 0);

   CONSTANT tCQ: TIME := 2.00000 ns;

   CONSTANT tCK: TIME := 30.3030 ns;
   CONSTANT tCH: TIME := 0.47 * tCK;
   CONSTANT tCL: TIME := 0.53 * tCK;

   FILE cmdfile: TEXT IS IN "fifo8-spew.dat";

   --"fifo8-spew.dat" line number
   SIGNAL line_number:  std_logic_vector(11 DOWNTO 0);

BEGIN

   --FIFO Design.
   fifo_1: fifo PORT MAP(
	    --module inputs
      wr_en=>wr_en, wr_clk=>wr_clk, reset=>reset, 
      rd_en=>rd_en, rd_clk=>rd_clk, din=>din,
	    --module outputs
      wr_count=>wr_count, full=>full, empty=>empty, 
      dout=>dout);


   PROCESS
      VARIABLE line_in: LINE;
      VARIABLE good: BOOLEAN;
      VARIABLE tmp_wr_en: std_ulogic;
      VARIABLE tmp_rd_en: std_ulogic;
      VARIABLE tmp_din: std_ulogic_vector(7 DOWNTO 0);
      VARIABLE tmp_wr_count: std_ulogic_vector(3 DOWNTO 0);
      VARIABLE tmp_empty: std_ulogic;
      VARIABLE tmp_full: std_ulogic;
      VARIABLE tmp_dout: std_ulogic_vector(7 DOWNTO 0);

   BEGIN

      reset <= '1';
      LOOP
	IF EndFile(cmdfile) THEN EXIT; END IF;
	ReadLine(cmdfile, line_in);
	NEXT WHEN line_in'LENGTH = 0;
	--Reset while reading lines starting with '.'
	IF '.' = line_in(1) AND line_in'LENGTH = 1 THEN EXIT; END IF;
	wr_clk <= '1';
	WAIT FOR tCH;
	wr_clk <= '0';
	WAIT FOR tCL;
      END LOOP;

      wr_clk <= '1';
      reset <= '0' AFTER tCQ;
      WAIT FOR tCH;
      wr_clk <= '0';
      WAIT FOR tCL;
      line_number <= "000000000000";

      LOOP
	IF EndFile(cmdfile) THEN EXIT; END IF;
	ReadLine(cmdfile, line_in);
	NEXT WHEN line_in'LENGTH = 0;

	wr_clk <= '1';

	  Read(line_in, tmp_wr_en, good);
	  ASSERT good REPORT "Reading wr-en" SEVERITY FAILURE;
	  wr_en <= To_StdLogic(tmp_wr_en) AFTER tCQ;

	  Read(line_in, tmp_rd_en, good);
	  ASSERT good REPORT "Reading rd-en" SEVERITY FAILURE;
	  rd_en <= To_StdLogic(tmp_rd_en) AFTER tCQ;

	  Read(line_in, tmp_din, good);
	  ASSERT good REPORT "Reading din[7:0]" SEVERITY FAILURE;
	  IF (good) THEN
	    din(7 DOWNTO 0) <= To_StdLogicVector(tmp_din) AFTER tCQ;
	  END IF;

	  Read(line_in, tmp_wr_count, good);
	  ASSERT good REPORT "Reading wr-count[3:0]" SEVERITY FAILURE;

	  Read(line_in, tmp_empty, good);
	  ASSERT good REPORT "Reading empty" SEVERITY FAILURE;

	  Read(line_in, tmp_full, good);
	  ASSERT good REPORT "Reading full" SEVERITY FAILURE;

	  Read(line_in, tmp_dout, good);
	  ASSERT good REPORT "Reading dout[7:0]" SEVERITY FAILURE;

	WAIT FOR tCH;
	  wr_clk <= '0';
	WAIT FOR tCL;

	  --Check outputs
	  ASSERT "UUUU" = tmp_wr_count
		OR "ZZZZ" = tmp_wr_count
		OR wr_count(3 DOWNTO 0) = To_StdLogicVector(tmp_wr_count)
	    REPORT "Mismatched wr-count[3:0]" SEVERITY ERROR;

	  ASSERT 'U' = tmp_empty
		 OR 'Z' = tmp_empty
		 OR empty = To_StdLogic(tmp_empty)
	    REPORT "Mismatched empty" SEVERITY ERROR;

	  ASSERT 'U' = tmp_full
		 OR 'Z' = tmp_full
		 OR full = To_StdLogic(tmp_full)
	    REPORT "Mismatched full" SEVERITY ERROR;

	  ASSERT "UUUUUUUU" = tmp_dout
		OR "ZZZZZZZZ" = tmp_dout
		OR dout(7 DOWNTO 0) = To_StdLogicVector(tmp_dout)
	    REPORT "Mismatched dout[7:0]" SEVERITY ERROR;

	line_number <= 1 + line_number;

      END LOOP;
      WAIT;
   END PROCESS;

END stimulus;