Hi, there!

Welcome to my personal website.
You can find information about me here.

Short bio:

I am a 5th-year Ph.D. student advised by Prof. Daniel Sanchez at MIT CSAIL. My research focuses on computer architecture and systems. Specifically, I work on memory hierarchy design, resource management in multi-core systems, and software/hardware co-optimization.

About my research:

Modern processors are much faster than their main memory. A multiply-and-add in a processor is >10x faster and takes >100x less energy than an access to its main memory. This makes applications stall and wait for data most of the time and spend a huge amount of energy on accessing it. Without a drastic reduction in data movement, memory accesses will limit the scalability of future systems.

My research focuses on two directions to reduce data movement:
1. how to better use faster, energy-efficient but scarce on-chip memories (i.e., caches), and
2. how to put computation closer to its data (i.e., near-data processing).
These techniques span across hardware and software, where flexible hardware components are exposed to intelligent system software to automatically optimize the system for users.

Apart from my main research, I have a broad interest in computer system performance, from warehouse-scale datacenters (workload scheduling in datacenters) to nano-scale devices (emerging memory technologies).

Last update: September, 2017

My CV

Here's my latest CV

Publications

Nexus: A New Approach to Replication in Distributed Shared Caches

Po-An Tsai, Nathan Beckmann, and Daniel Sanchez.
The 26th Intl' Conference on Parallel Architectures and Compilation Techniques (PACT-26), September 2017.
[paper] [talk]

Jenga: Software-Defined Cache Hierarchies

Po-An Tsai, Nathan Beckmann, and Daniel Sanchez.
The 44th International Symposium on Computer Architecture (ISCA-44), June 2017.
[paper] [talk] [tech-report] [MIT news]

Scaling Non-Uniform Cache Architectures with Computation and Data Co-Scheduling

Nathan Beckmann, Po-An Tsai, and Daniel Sanchez.
The 21st International Symposium on High Performance Computer Architecture (HPCA-21), February 2015.
*Nominated for best paper award
[paper] [talk] [MIT news]

Hybrid Path-Diversity-Aware Adaptive Routing with Latency Prediction Model in Network-on-Chip Systems

Po-An Tsai, Yu-Hsin Kuo, En-Jui Chang, and An-Yeu Wu.
2013 International Symposium on VLSI Design, Automation and Test, (VLSI-DAT), March 2013.
[paper]

Path-Diversity-Aware Adaptive Routing in Network-on-Chip Systems

Yu-Hsin Kuo, Po-An Tsai, Hao-Ping Ho, En-Jui Chang, Hsien-Kai Hsin, and An-Yeu Wu.
The 6th International Symposium on Embedded Multicore SoCs (MCSoC), September 2012.
[paper]

Contact Me

Office: 32 vassar street G888, Cambridge, MA, 02139

Email: poantsai@csail.mit.edu

Phone: 617-401-5389

Miscellaneous

A MIT news about Jenga

A Hacker News discussion on Jenga

A MIT news about CDCS

A Techenablement article about CDCS

The Industry-Academia Partnership (IAP) post about my best poster award in an IAP Cloud Workshop at MIT