Short bio:

I am a final-year Ph.D. student advised by Prof. Daniel Sanchez at MIT CSAIL. My research focuses on computer system and architecture. Specifically, I work on memory hierarchy design, resource management in multi-core systems, and software/hardware co-optimization. I am currently exploring full-time position starting 2019 spring/summer.

About my research:

Modern processors are much faster than their main memory. A multiply-and-add in a processor is >10x faster and takes >100x less energy than an access to its main memory. This makes applications stall and wait for data most of the time and spend a huge amount of energy on accessing it. Without a drastic reduction in data movement, memory accesses will limit the scalability of future systems.

My research focuses on two directions to reduce data movement:
  1. object-based memory hierarchies that better suited for modern languages, and
  2. specialized memory hierarchies that automatically adapt to workloads

My research spans across hardware and software, including architecture, automatic memory management, system runtime, and optimization algorithms.

Apart from my main research, I have a broad interest in computer system performance, from warehouse-scale datacenters (workload scheduling in datacenters) to nano-scale devices (emerging memory technologies).

Last update: September 2018

CV and Resume

Here are my latest CV and resume

Publications

Compress Objects, Not Cache Lines: An Object-Based Compressed Memory Hierarchy

Po-An Tsai and Daniel Sanchez.
The 24th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-24), April 2019 (to appear).
[paper] [talk]

Rethinking the Memory Hierarchy for Modern Languages

Po-An Tsai, Yee Ling Gan, and Daniel Sanchez.
The 51st IEEE/ACM International Symposium on Microarchitecture (MICRO-51), October 2018.
[paper] [talk] [poster] [lightning]

Adaptive Scheduling for Systems with Asymmetric Memory Hierarchies

Po-An Tsai, Changping Chen, and Daniel Sanchez.
The 51st IEEE/ACM International Symposium on Microarchitecture (MICRO-51), October 2018.
[paper] [talk] [poster] [lightning]

KPart: A Hybrid Cache Partitioning-Sharing Technique for Commodity Multicores

Nosayba El-Sayed, Anurag Mukkara, Po-An Tsai, Harshad Kasture, Xiaosong Ma, and Daniel Sanchez.
The 24th Intl' Symposium on High Performance Computer Architecture (HPCA-24), February 2018.
[paper] [talk] [code]

Nexus: A New Approach to Replication in Distributed Shared Caches

Po-An Tsai, Nathan Beckmann, and Daniel Sanchez.
The 26th Intl' Conference on Parallel Architectures and Compilation Techniques (PACT-26), September 2017.
[paper] [talk]

Jenga: Software-Defined Cache Hierarchies

Po-An Tsai, Nathan Beckmann, and Daniel Sanchez.
The 44th International Symposium on Computer Architecture (ISCA-44), June 2017.
[paper] [talk] [tech-report] [MIT news]

Scaling Distributed Cache Hierarchies through Computation and Data Co-Scheduling

Nathan Beckmann, Po-An Tsai, and Daniel Sanchez.
The 21st Intl' Symposium on High Performance Computer Architecture (HPCA-21), February 2015.
*Nominated for best paper award
[paper] [talk] [MIT news]

Hybrid Path-Diversity-Aware Adaptive Routing with Latency Prediction Model in Network-on-Chip Systems

Po-An Tsai, Yu-Hsin Kuo, En-Jui Chang, and An-Yeu Wu.
2013 International Symposium on VLSI Design, Automation and Test, (VLSI-DAT), March 2013.
[paper]

Path-Diversity-Aware Adaptive Routing in Network-on-Chip Systems

Yu-Hsin Kuo, Po-An Tsai, Hao-Ping Ho, En-Jui Chang, Hsien-Kai Hsin, and An-Yeu Wu.
The 6th International Symposium on Embedded Multicore SoCs (MCSoC), September 2012.
[paper]

Contact Me

Office: 32 vassar street G888, Cambridge, MA, 02139

Email: poantsai@csail.mit.edu

Phone: 617-401-5389

Press

MIT news about Jenga

Hacker News discussion on Jenga

MIT news about CDCS

Techenablement article about CDCS

The Industry-Academia Partnership (IAP) post about my best poster award