Presents a novel high-level synthesis algorithm for complex pipelined circuits, including pipelined circuits with feedback, and the synthesis algorithm that makes the approach viable in practice. The designer specifies the circuit as a set of independent modules connected by conceptually unbounded queues. The synthesis algorithm automatically transforms the modular, asynchronous specification into a tightly coupled, fully synchronous implementation in synthesizable Verilog.
Presents a synthesis algorithm for pipelined circuits consisting of modules connected by finite-length buffers.
Presents a novel compilation system that allows sequential programs, written in C or FORTRAN, to be compiled directly into custom silicon or reconfigurable architectures. The compiler first analyzes the memory access patterns of pointers and arrays in the program and constructs a partitioned memory system made up of many small memories. The computation is implemented by active computing elements that are spatially distributed within the memory array. A space-time scheduler assigns instructions to the computing elements in a way that maximizes locality and minimizes physical communication distance. It also generates an efficient static schedule for the interconnect. Finally, specialized hardware for the resulting schedule of memory accesses, wires, and computation is generated as a multi-process state machine in synthesizable Verilog.