module Mcluster 
	(reset,
	 ext_d_xportC0_np, ext_d_xportC1_np, ext_d_xportC2_np, ext_d_xportC3_np, ext_d_dox_in_np,
	 d_xport_send_in_np, wX_recv_in_np) 
	(ext_wX_out_np, wX_send_out_np, d_xport_recv_out_np) {
   
  wire const enable_always = 1;

  wire f_ctrl_en_np, f_ctrl_iqc_update_np, f_ctrl_recv_en_np;
  wire 46 f_inst_np, d_inst_np;

  wire d_ctrl_recv_en_np;
  wire 5 d_ctrl_rs_np, d_ctrl_rt_np, d_ctrl_rd_np, x_ctrl_rd_np, x_ctrl_rd_pn;
  wire 8 d_ctrl_exe_np, x_ctrl_exe_np;
  wire d_ctrl_xport_recv_np, dX_ctrl_send_np, d_ctrl_regwr_np, d_ctrl_xport_dox_in_np;
  wire 2 d_ctrl_rs_src_np, d_ctrl_rt_src_np, d_ctrl_xport_csrc_np;
  wire 5 dX_ctrl_dst_np, xX_ctrl_dst_np;

  wire 2 d_ctrl_rs_src_pn, d_ctrl_rt_src_pn;

  wire 5 x_ctrl_aluop_np, x_ctrl_shamt_np;
  wire x_ctrl_sh_right_np, x_ctrl_sh_logical_np, x_ctrl_aluorsh_np;

  wire d_ctrl_regwr_alive_np, x_ctrl_regwr_alive_np, x_ctrl_regwr_alive_pn,
    d_ctrl_alive_np, x_ctrl_alive_np,
    dX_ctrl_send_alive_np, xX_ctrl_send_alive_np, wX_ctrl_send_alive_np;

  wire d_ctrl_recv_active_np, d_xport_in_ll_en_np, d_recv_done_np, wX_send_done_np;
  wire dX_ctrl_en_np, xX_ctrl_en_np;

  wire 8 d_ctrl_rs_mux_pn, d_ctrl_rt_mux_pn;
  wire 8 d_ctrl_xport_in_mux1_np;
  wire 2 d_ctrl_xport_in_mux2_np, x_ctrl_result_mux_np;

  wire 8 d_inst_immed_np, d_inst_immed_pn;
  wire 32 d_immed_ext_pn;

  wire 5 xX_send_out_np;

  wire 14 x_ctrl_alu_np;
  wire monitor 21 x_ctrl_shifter_np;

  wire 32 d_xportC0_np, d_xportC1_np, d_xportC2_np, d_xportC3_np, d_dox_in_np;

  wire 32 d_rx_p, d_ry_p, d_rx_pn, d_ry_pn;
  wire 32 d_rs_pn, d_rt_pn;
  wire 32 d_xport_in1_np, d_xport_in2_np, d_xport_in_pn;
  wire 32 x_rs_np, x_rt_np;
  wire 32 x_alu_p, x_shifter_np, x_result_p;
  wire 32 x_result_pn;
  wire 32 wX_out_np;
  wire monitor x_taken_p, x_ovf_p;
   


  /***********************************************************************\
   *			           F STAGE     			         *
  \***********************************************************************/

  f_iqc { (CLK-P.EvalUpdate, CLK-L.EvalRead) DXC_IQC } (f_ctrl_iqc_update_np) (f_inst_np);

  /////////////////////////////////////////////////////////////////////////
  d_inst_pf { P-CLK DXC_PFF_En<46> } (f_inst_np, f_ctrl_en_np) (d_inst_np);
  d_recv_en_pf { P-CLK DXC_PFF<1> } (f_ctrl_recv_en_np) (d_ctrl_recv_en_np);
  /////////////////////////////////////////////////////////////////////////

  /***********************************************************************\
   *			           D STAGE     			         *
  \***********************************************************************/

  assign d_ctrl_rs_np	 	= d_inst_np[4:0];
  assign d_ctrl_rt_np 	 	= d_inst_np[9:5];
  assign d_ctrl_rd_np 	 	= d_inst_np[14:10];
  assign d_ctrl_exe_np 	 	= d_inst_np[22:15];
  assign d_ctrl_xport_recv_np 	= d_inst_np[23];
  assign dX_ctrl_send_np 	= d_inst_np[24];
  assign d_ctrl_regwr_np	= d_inst_np[25];
  assign d_ctrl_rs_src_np	= d_inst_np[27:26];
  assign d_ctrl_rt_src_np 	= d_inst_np[29:28];
  assign d_ctrl_xport_csrc_np 	= d_inst_np[31:30];
  assign d_ctrl_xport_dox_in_np	= d_inst_np[32];
  assign dX_ctrl_dst_np 	= d_inst_np[37:33];
  assign d_inst_immed_np	= d_inst_np[45:38];

  d_regfile { (CLK-P.EvalWrite, CLK-L.EvalRead) DXC_RegFile<32, 32, 5> } 
	(d_ctrl_rs_np, enable_always, d_ctrl_rt_np, enable_always, 
	 x_ctrl_rd_pn, x_ctrl_regwr_alive_pn, x_result_pn) 
	(d_rx_p, d_ry_p); 

  d_ctrl_recv_active { DXC_And2 } (d_ctrl_recv_en_np, d_ctrl_xport_recv_np) (d_ctrl_recv_active_np);

  d_xport_recv_out { DXC_Xport_Recv_Out } 
	(d_ctrl_xport_dox_in_np, d_ctrl_xport_csrc_np, d_ctrl_recv_active_np) 
	(d_xport_recv_out_np);

  d_xport_recv_done { DXC_Xport_Done } 
	(d_xport_recv_out_np, d_xport_send_in_np) 
	(d_recv_done_np);

  assign d_xportC0_np = ext_d_xportC0_np;
  assign d_xportC1_np = ext_d_xportC1_np;
  assign d_xportC2_np = ext_d_xportC2_np;
  assign d_xportC3_np = ext_d_xportC3_np;
  assign d_dox_in_np = ext_d_dox_in_np;

  d_xport_in_mux1_decoder { DXC_Mux4_Decoder } (d_ctrl_xport_csrc_np) (d_ctrl_xport_in_mux1_np);
  d_xport_in_mux1 { DXC_Mux4<32> } 
	(d_xportC0_np, d_xportC1_np, d_xportC2_np, d_xportC3_np, d_ctrl_xport_in_mux1_np) 
	(d_xport_in1_np);

  d_xport_in_mux2_decoder { DXC_Mux2_Decoder } (d_ctrl_xport_dox_in_np) (d_ctrl_xport_in_mux2_np);
  d_xport_in_mux2 { DXC_Mux2<32> } 
	(d_xport_in1_np, d_dox_in_np, d_ctrl_xport_in_mux2_np) 
	(d_xport_in2_np);

  /////////////////////////////////////////////////////////////////////////
  d_ctrl_rs_src_ll { L-LATCH DXC_LL<2> } (d_ctrl_rs_src_np) (d_ctrl_rs_src_pn);
  d_ctrl_rt_src_ll { L-LATCH DXC_LL<2> } (d_ctrl_rt_src_np) (d_ctrl_rt_src_pn);
  d_immed_ll { L-LATCH DXC_LL<8> } (d_inst_immed_np) (d_inst_immed_pn);
  d_rx_ll { L-LATCH DXC_LL<32> } (d_rx_p) (d_rx_pn);
  d_ry_ll { L-LATCH DXC_LL<32> } (d_ry_p) (d_ry_pn);
  d_xport_in_ll { (CLK-N.ClkGate, CLK-L.Evaluate) DXC_Latch_En<32> } 
	(d_xport_in2_np, d_xport_in_ll_en_np) (d_xport_in_pn);
  /////////////////////////////////////////////////////////////////////////

  d_immed_ext { DXC_SignExtend<8,32> } (d_inst_immed_pn) (d_immed_ext_pn);

  d_rs_mux_decoder { DXC_Mux4_Decoder } (d_ctrl_rs_src_pn) (d_ctrl_rs_mux_pn);
  d_rt_mux_decoder { DXC_Mux4_Decoder } (d_ctrl_rt_src_pn) (d_ctrl_rt_mux_pn);

  d_rs_mux { DXC_Mux4<32> } (d_rx_pn, x_result_pn, d_immed_ext_pn, d_xport_in_pn, d_ctrl_rs_mux_pn) (d_rs_pn);
  d_rt_mux { DXC_Mux4<32> } (d_ry_pn, x_result_pn, d_immed_ext_pn, d_xport_in_pn, d_ctrl_rt_mux_pn) (d_rt_pn);

  /////////////////////////////////////////////////////////////////////////
  x_rs_hl { H-LATCH DXC_HL<32> } (d_rs_pn) (x_rs_np);
  x_rt_hl { H-LATCH DXC_HL<32> } (d_rt_pn) (x_rt_np);
  x_ctrl_exe_pf		{ P-CLK DXC_PFF<8> } (d_ctrl_exe_np)		(x_ctrl_exe_np);
  x_ctrl_rd_pf 		{ P-CLK DXC_PFF<5> } (d_ctrl_rd_np)		(x_ctrl_rd_np);
  x_ctrl_regwr_pf 	{ P-CLK DXC_PFF<1> } (d_ctrl_regwr_alive_np)	(x_ctrl_regwr_alive_np);
  x_ctrl_alive_pf 	{ P-CLK DXC_PFF<1> } (d_ctrl_alive_np)		(x_ctrl_alive_np);
  xX_ctrl_send_alive_pf	{ P-CLK DXC_PFF_En<1>} (dX_ctrl_send_alive_np, dX_ctrl_en_np) (xX_ctrl_send_alive_np);
  xX_ctrl_xport_dst_pf 	{ P-CLK DXC_PFF_En<5>} (dX_ctrl_dst_np,        dX_ctrl_en_np) (xX_ctrl_dst_np);
  /////////////////////////////////////////////////////////////////////////

  /***********************************************************************\
   *			           X STAGE			         *       
  \***********************************************************************/


  assign x_ctrl_aluop_np = x_ctrl_exe_np[4:0];
  assign x_ctrl_shamt_np = x_ctrl_exe_np[4:0];
  assign x_ctrl_sh_right_np = x_ctrl_exe_np[5];
  assign x_ctrl_sh_logical_np = x_ctrl_exe_np[6];
  assign x_ctrl_aluorsh_np = x_ctrl_exe_np[7];

  x_alu_ctrl { DXC_ALU_Ctrl } (x_ctrl_aluop_np) (x_ctrl_alu_np);

  x_alu { (CLK-H.Precharge, CLK-L.Evaluate) DXC_ALU } 
	(x_rs_np, x_rt_np, x_ctrl_alu_np, enable_always) 
	(x_alu_p, x_taken_p, x_ovf_p);

  x_shifter_ctrl { DXC_Shifter_Ctrl } 
	(x_ctrl_shamt_np, x_ctrl_sh_right_np, x_ctrl_sh_logical_np) 
	(x_ctrl_shifter_np);

  x_shifter { DXC_Shifter<32,5> } 
	(x_rt_np, x_ctrl_shamt_np, x_ctrl_sh_right_np, x_ctrl_sh_logical_np) 
	(x_shifter_np);

  x_result_mux_decoder { DXC_Mux2_Decoder } (x_ctrl_aluorsh_np) (x_ctrl_result_mux_np);

  x_result_mux { DXC_Mux2<32> } (x_alu_p, x_shifter_np, x_ctrl_result_mux_np) (x_result_p);

  xX_send_out { DXC_Xport_Out } 
	(xX_ctrl_dst_np, xX_ctrl_send_alive_np) (xX_send_out_np);

  /////////////////////////////////////////////////////////////////////////
  x_result_ll		{ (CLK-N.ClkGate, CLK-L.Evaluate) DXC_Latch_En<32> } (x_result_p, x_ctrl_alive_np) (x_result_pn);
  x_ctrl_regwr_ll 	{ L-LATCH DXC_LL<1> } (x_ctrl_regwr_alive_np)	   (x_ctrl_regwr_alive_pn);
  x_ctrl_rd_ll 		{ L-LATCH DXC_LL<5> } (x_ctrl_rd_np) 	 	   (x_ctrl_rd_pn);
  /////////////////////////////////////////////////////////////////////////

  /////////////////////////////////////////////////////////////////////////
  wX_out_hl		{ (CLK-P.ClkGate, CLK-H.Evaluate) DXC_Latch_En<32> }
						(x_result_pn,           xX_ctrl_en_np) (wX_out_np);
  wX_send_out_pf	{P-CLK DXC_PFF_En<5>}	(xX_send_out_np,        xX_ctrl_en_np) (wX_send_out_np);
  wX_ctrl_send_alive_pf {P-CLK DXC_PFF_En<1>}	(xX_ctrl_send_alive_np, xX_ctrl_en_np) (wX_ctrl_send_alive_np);
  /////////////////////////////////////////////////////////////////////////

  /***********************************************************************\
   *			            W STAGE			         *       
  \***********************************************************************/

  wX_send_done { DXC_Xport_Done } 
	(wX_send_out_np, wX_recv_in_np) 
	(wX_send_done_np);

  assign ext_wX_out_np = wX_out_np;

  /***********************************************************************\
  \***********************************************************************/

  pipectrl { DXC_PipeCtrl }
	(reset,
	 d_ctrl_recv_active_np, d_recv_done_np, 
	 wX_ctrl_send_alive_np, wX_send_done_np,
	 d_ctrl_regwr_np, dX_ctrl_send_np,
	 xX_ctrl_send_alive_np)	
	(f_ctrl_en_np, f_ctrl_iqc_update_np, f_ctrl_recv_en_np,
	 d_ctrl_alive_np,
	 d_ctrl_regwr_alive_np,
	 d_xport_in_ll_en_np,
	 dX_ctrl_send_alive_np,
	 dX_ctrl_en_np,
	 xX_ctrl_en_np);

};