dox-begin C0 sll 0  immed 1		     -> xport-out-dox	
dox-begin C1 sll 0  immed 0		     -> xport-out-dox	
dox-begin C2 sll 0  immed 0		     -> xport-out-dox	
dox-begin C3 sll 0  immed 0		     -> xport-out-dox	

vector	  C0 addu   xport-in-dox  immed 0    -> reg 0 xport-out-dox
vector	  C0 sll 0  byp			     -> xport-out-cluster 1
vector	  C1 sll 0  xport-in-cluster 0	     -> 
vector	  C1 addu   byp xport-in-dox	     -> reg 0 xport-out-dox
vector	  C1 sll 0  byp			     -> xport-out-cluster 2
vector	  C2 sll 0  xport-in-cluster 1	     -> 
vector	  C2 addu   byp xport-in-dox	     -> reg 0 xport-out-dox
vector	  C2 sll 0  byp			     -> xport-out-cluster 3
vector	  C3 sll 0  xport-in-cluster 2	     -> 
vector	  C3 addu   byp xport-in-dox	     -> reg 0 xport-out-dox

vector	  C0 addu   xport-in-dox  immed 0    -> reg 1 xport-out-dox
vector	  C0 sll 0  byp			     -> xport-out-cluster 1
vector	  C1 sll 0  xport-in-cluster 0	     -> 
vector	  C1 addu   byp xport-in-dox	     -> reg 1 xport-out-dox
vector	  C1 sll 0  byp			     -> xport-out-cluster 2
vector	  C2 sll 0  xport-in-cluster 1	     -> 
vector	  C2 addu   byp xport-in-dox	     -> reg 1 xport-out-dox
vector	  C2 sll 0  byp			     -> xport-out-cluster 3
vector	  C3 sll 0  xport-in-cluster 2	     -> 
vector	  C3 addu   byp xport-in-dox	     -> reg 1 xport-out-dox

vector	  C0 addu   xport-in-dox  immed 0    -> reg 2 xport-out-dox
vector	  C0 sll 0  byp			     -> xport-out-cluster 1
vector	  C1 sll 0  xport-in-cluster 0	     -> 
vector	  C1 addu   byp xport-in-dox	     -> reg 2 xport-out-dox
vector	  C1 sll 0  byp			     -> xport-out-cluster 2
vector	  C2 sll 0  xport-in-cluster 1	     -> 
vector	  C2 addu   byp xport-in-dox	     -> reg 2 xport-out-dox
vector	  C2 sll 0  byp			     -> xport-out-cluster 3
vector	  C3 sll 0  xport-in-cluster 2	     -> 
vector	  C3 addu   byp xport-in-dox	     -> reg 2 xport-out-dox

vector	  C0 addu   xport-in-dox  immed 0    -> reg 3 xport-out-dox
vector	  C0 sll 0  byp			     -> xport-out-cluster 1
vector	  C1 sll 0  xport-in-cluster 0	     -> 
vector	  C1 addu   byp xport-in-dox	     -> reg 3 xport-out-dox
vector	  C1 sll 0  byp			     -> xport-out-cluster 2
vector	  C2 sll 0  xport-in-cluster 1	     -> 
vector	  C2 addu   byp xport-in-dox	     -> reg 3 xport-out-dox
vector	  C2 sll 0  byp			     -> xport-out-cluster 3
vector	  C3 sll 0  xport-in-cluster 2	     -> 
vector	  C3 addu   byp xport-in-dox	     -> reg 3 xport-out-dox

dox-end   C0 sll 0  xport-in-dox	     -> 
dox-end   C1 sll 0  xport-in-dox	     -> 
dox-end   C2 sll 0  xport-in-dox	     -> 
dox-end   C3 sll 0  xport-in-dox	     ->