Larry Rudolph's comments microprocessor caches (back to home page)

There is lots of stuff here.

Derek Chiou did his thesis on column and curious caching.

Ed Suh did a lot of stuff on modeling ceches in an interactive, multitasking environments.

David Chen completed an MEng thesis that investigates compressing the L2 cache. It uses a dictionary and so cache lines can be compressed or decompressed one at a time (rather than the whole cache). More exciting is items are stored either compressed or not depending on the frequency of access -- a frequently accessed item is not compressed --> -- but if there are some less frequently accessed items in the L2, --> -- then by compressing them, some memory accesses might be avoided. (When I put the thesis online, I will add a link to it.)