Sizhuo Zhang Department of EECS Massachusetts Institute of Technology 32 Vassar Street, G888, Cambridge, MA, 02139 Email: szzhang@mit.edu, szzhang@csail.mit.edu, zhang_si_zhuo@hotmail.com, szzhang@alum.mit.edu

About Me

I got my PhD from MIT Computer Science and Artificial Intelligence Laboratory. I am advised by Professor Arvind. My research focuses on weak memory consistency models for multicores, and corresponding processor prototypes on FPGA using the RISC-V instruction set. Our work on the RISC-V out-of-order multiprocessor has been selected for IEEE Micro Top Picks from the 2018 Computer Architecture Conferences. The source code for the processor is now available on github.

Before joining MIT, I received my Bechelor degree from the Department of Microelectronics and Nanoelectronics in Tsinghua University.

Here is my resume (09/2018).

Update 06/2019: I have graduated and joined Apple. My MIT email accounts will expire soon. Please contact me at zhang_si_zhuo@hotmail.com or szzhang@alum.mit.edu.

Conference Papers

• MI6: Secure Enclaves in a Speculative Out-of-Order Processor [pdf]
  Thomas Bourgeat*, Ilia Lebedev*, Andrew Wright*, Sizhuo Zhang*, Arvind, Srinivas Devadas
  The 52nd IEEE/ACM International Symposium on Microarchitecture (MICRO), October 2019
  *Student authors are listed in alphabetical order
  

• Composable Building Blocks to Open up Processor Design [pdf]
  Sizhuo Zhang, Andrew Wright, Thomas Bourgeat, Arvind
  The 51st IEEE/ACM International Symposium on Microarchitecture (MICRO), October 2018
  - Selected for IEEE Micro Top Picks from the 2018 Computer Architecture Conferences
  - Source codes for the out-of-order processor are available at https://github.com/csail-csg/riscy-OOO
  

• Constructing a Weak Memory Model [pdf*]
  Sizhuo Zhang, Muralidaran Vijayaraghavan, Andrew Wright, Mehdi Alipour, Arvind
  The 45th International Symposium on Computer Architecture (ISCA), June 2018
  *Fixed typo in Figure 9.
  

• GraFBoost: Accelerated Flash Storage for External Graph Analytics [pdf]
  Sang Woo Jun, Andrew Wright, Sizhuo Zhang, Shuotao Xu, Arvind
  The 45th International Symposium on Computer Architecture (ISCA), June 2018
  

• HGum: Messaging Framework for Hardware Accelerators [pdf]
  Sizhuo Zhang, Hari Angepat, Derek Chiou
  2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig), December 2017
  

• Weak Memory Models: Balancing Definitional Simplicity and Implementation Flexibility [pdf (extended version)]
  Sizhuo Zhang, Muralidaran Vijayaraghavan, Arvind
  The 26th International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2017
  

Journal Paper

• Composable Building Blocks to Open up Processor Design
  Sizhuo Zhang, Andrew Wright, Thomas Bourgeat, Arvind
  IEEE Micro, Volume 39, Issue 3, May-June 2019
  

• Proteus: Language and Runtime Support for Self-Adaptive Software Development
  Many authors
  IEEE Software, Volume 36, Issue 2, March-April 2019
  

Technical Reports

• MI6: Secure Enclaves in a Speculative Out-of-Order Processor
  Thomas Bourgeat*, Ilia Lebedev*, Andrew Wright*, Sizhuo Zhang*, Arvind, Srinivas Devadas
  arXiv:1812.09822
  *Student authors are listed in alphabetical order
  

• Weak Memory Models with Matching Axiomatic and Operational Definitions
  Sizhuo Zhang, Muralidaran Vijayaraghavan, Dan Lustig, Arvind
  arXiv:1710.04259
  

• An Operational Framework for Specifying Memory Models using Instantaneous Instruction Execution
  Sizhuo Zhang, Muralidaran Vijayaraghavan, Arvind
  arXiv:1705.06158
  

• Taming Weak Memory Models
  Sizhuo Zhang, Arvind, Muralidaran Vijayaraghavan
  arXiv:1606.05416
  

• WMM: a Resilient Weak Memory Model
  Sizhuo Zhang
  Master Thesis, MIT EECS

• Validating Simplified Processor Models in Architectural Studies
  Sizhuo Zhang, Andrew Wright, Daniel Sanchez, Arvind
  arXiv:1610.02094
  

Poster

• HGum: Messaging Framework for Hardware Accelerators [Abstract]
  Sizhuo Zhang, Hari Angepat, Derek Chiou
  24th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, February, 2016

Talk

• Weak Memory Models: Balancing Definitional Simplicity and Implementation Flexibility
  Dagstuhl Seminar 16471: "Concurrency with Weak Memory Models: Semantics, Languages, Compilation, Verification, Static Analysis, and Synthesis", November, 2016.

Media Coverage

• Opening up open-source to design better chips
  MIT CSAIL News, Oct 22, 2018

• Device allows a personal computer to process huge graphs
  MIT News, May 31, 2018