Muralidaran Vijayaraghavan

I am a graduate student at MIT. Before coming here, I was an undergraduate at the Indian Institute of Technology, Madras. Madras (or rather Chennai) is also the city I grew up in.

Research Interests

I am interested in computer architecture and parallel programming. My advisor is Professor Arvind. Recently, I've been working on performance modeling of systems using FPGAs.

Recent Publications

  • Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs

    • with Michael Pellauer, Michael Adler, Arvind and Joel Emer
    in ISPASS, 2008
    In this paper we describe how performance models can be partitioned in order to allow easy reuse of code for microarchitectural exploration

  • A-Ports: An Efficient Abstraction for Cycle-Accurate Performance Models on FPGAs

    • with Michael Pellauer, Michael Adler, Arvind and Joel Emer
    in ISFPGA, 2008
    In this paper we describe how performance models can keep track of simulation time in a distributed fashion

Friends Swarm

This page was blatantly copied from Rajsekar.

Contact

Address:
Computer Science and Artificial Intelligence Lab
The Stata Center
Massachusetts Institute of Technology
32 Vassar Street, 32-G836
Cambridge, MA 02139

Email: {first_character_of_my_last_name}{first_six_characters_of_my_first_name} at csail dot mit dot edu

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