My research is between computer architecture and programming languages.
I work on leveraging high-level hardware programming languages to design hardware.
I am especially interested in leveraging those hardware programming languages to ease verification, which is typically a significant part of the development effort.
Especially, I often try to use theorem proving to state and prove the properties of different architectures.
In the past, I worked on domain-specific hardware accelerators and I studied various unintended security consequences of modern microarchitectural features in our out-of-order processor (see our riscy-OOO project).
I am actively recruiting PhD students and postdocs.
If you are a prospective PhD student interested in this kind of research, please apply.
CV as of 03/2021.
Selected publications
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ASPLOS2022
DAGguise: Mitigating Memory Timing Side Channels
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ISCA2021
FlexMiner: A Pattern-Aware Accelerator for Graph Pattern Mining
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ICRA2021
Accelerating Robot Dynamics Gradients: Hardware-Sofware Co-Design on a CPU, GPU, and FPGA
[pdf] -
ASPLOS2021
Effective Simulation and Debugging for High-Level Hardware Languages Using Software Compilers
[pdf] -
ASPLOS2021
Robomorphic Computing: A Design Methodology for Domain-Specific Accelerators Parameterized by Robot Morphology
[pdf] -
MICRO2020
CaSA: End-to-end Quantitative Security Analysis of Randomly Mapped Caches
[pdf] -
MICRO2020
AQUOMAN An Analytic-Query Offloading Machine
[pdf] -
PLDI2020
The essence of Bluespec: a core language for rule-based hardware design
[pdf] -
MICRO2019
MI6: Secure Enclaves in a Speculative Out-of-Order Processor
[pdf] -
MICRO2018
Composable Building Blocks to Open up Processor Design
[pdf] -
ASYNC2016
Specification mining for asynchronous controllers
[pdf]