Charles E

Charles E. Leiserson

Professor, Electrical Engineering and Computer Science

Education:

School	Degree	Date
Yale University	B.S. (cum laude)	May 1975
Carnegie-Mellon University	Ph.D	December 1981

MIT Appointments:

Rank	Beginning	Ending
Assistant Professor	January 1981	June 1984
Associate Professor	July 1984	June 1988
Associate Professor with Tenure	July 1988	June f1992
Full Professor	July 1992	present

Other Related Experience (most recent):

Employer	Position	Beginning	Ending
Max Planck Institute für Informatik	Fachbeirat (Visiting Committee)	Sept. 1992	present
Ecole Normale Superieure de Lyon	Visiting Professor	June 1993	July 1993
National University of Singapore	Shaw Visiting Professor	August 1995	August 1996
Akamai Technologies	Director of System Architecture	June 1999	present

Consulting & Patents (partial list):

Firm	Beginning	Ending
National University of Singapore, Adjunct Professor	Sept. 1996	present
NKK Corporation	March 1997	March 1997
Pratt & Whitney	May 1997	Dec. 1999
EMC² Corporation	June 1998	Dec. 1999
Akamai Technologies	June 1999	present

H. T. Kung and Charles E. Leiserson, "Systolic array apparatus for matrix computations,'' U.S. Patent 494,659, March 29, 1984.

Thomas H. Cormen and Charles E. Leiserson, "A message merging device,'' U.S. Patent 4,922,246, May 1, 1990.

Robert C. Zak, Charles E. Leiserson, Bradley C. Kuszmaul, ShawWen Yang, W. Daniel Hillis, David C. Douglas, and David Potter, "Parallel computer system including arrangement for transferring messages from a source processor to selected ones of a plurality of destination processors and combining responses,'' U.S. Patent 5,265,207, November 23, 1993.

Charles E. Leiserson, Robert C. Zak, W. Daniel, Hillis, Bradley C. Kuszmaul, Jeffrey V. Hill, "Parallel computer system including request distribution network for distributing processing requests to selected sets of processors in parallel,'' U.S. Patent 5,388,214, February 7, 1995.

Bradley C. Kuszmaul, Charles E. Leiserson, ShawWen Yang, Carl R. Feynman, W. Daniel Hillis, David Wells, Cynthia J. Spiller, "Parallel computer system including arrangement for quickly draining messages from message router,'' U. S. Patent 5,390,298, February 14, 1995.