Direct Execution b Processor (Can we get rid of slow interpreters?)

3/31/98


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Table of Contents

Direct Execution b Processor (Can we get rid of slow interpreters?)

6.004 Processors and ISA’s: Big Picture

Performance Measure

b Performance Options

b Instruction Set Architecture

Approach: Incremental Design

Datapath Components

2-Port Register File

ALU Register-Register Operations

ALU Register-Constant Operations

Load Instruction

Store Instruction

Jump Instruction

Branch Instructions

Load Relative Instruction

What’s LDR Good For Anyway?

Exceptions: Traps, Faults and Interrupts

Specifying Combinational Control Logic

Next Time: Pipelined b Processor

Unpipelined b Implementation

Author: Srinivas Devadas

Email: devadas@mit.edu

Home Page: http://cag-www.lcs.mit.edu/6.004

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