Answer: Multilevel Memory

Strategy: Hide latency using small, fast memories called caches.

Caches are a mechanism to hide memory latency based on the empirical observation that the stream of memory references made by a processor exhibits .

PC

… 96

loop: MUL(r1, r0, r1) 100

SUB(r0, 1, r0) 104

BNE(r0, loop) 108

… 112

of instruction

memory addresses?

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