Write Buffers

M1

M2

WB

WB

y

x

Write buffer

x = 1 and y = 1 cached initially

Pi

Pj

Post

write x

read y

Post

write y

read x

Because of write buffer delay, cache

entries are not invalidated. Both hit

respective caches and return 1.

1

1

Snoopy

Cache

Snoopy

Cache

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