Instruction-Level Parallelism
Data Dependence Graph
Compiled Assembly Code
4-Stage b Pipeline
Load Bypass Paths
Avoiding Stalls
Questions
Accounting for Load Latency
Realizing CPI < 1.0
VLIW Architecture
Superscalar Architecture
Superpipelined Architecture
Architecture Characteristics
Branches
Speculative Execution
Implementation
Next Time: State-of-the-Art
Email: devadas@mit.edu
Home Page: http://cag-www.lcs.mit.edu/6.004
Download presentation postscript