Instruction-Level Parallelism

5/12/98


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Table of Contents

Instruction-Level Parallelism

Data Dependence Graph

Compiled Assembly Code

4-Stage b Pipeline

Load Bypass Paths

Avoiding Stalls

Questions

Instruction-Level Parallelism

Accounting for Load Latency

Realizing CPI < 1.0

VLIW Architecture

Superscalar Architecture

Superpipelined Architecture

Architecture Characteristics

Branches

Speculative Execution

Implementation

Next Time: State-of-the-Art

Author: Srinivas Devadas

Email: devadas@mit.edu

Home Page: http://cag-www.lcs.mit.edu/6.004

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