Feedback and State
Recap: Combinational Synthesis
Motivation: Adding a column of numbers
Implementing State
Implementing State - II
Solutions
Forcing a 0 or a 1
S-R Latch Timing
Timing Rule
D-Latch or Transparent Latch
Simplified D-Latch
How do we fix it?
Fixed D-latch
Timing of D-Latch
Setup and Hold Times
Edge-Triggered Flip-Flop
Timing of Edge-Triggered Flip-Flop
Latches and Flip-Flops
Latch 2 Hold Time (details in recitation)
Next Time: Finite State Machines
Email: devadas@mit.edu
Home Page: http://cag-www.lcs.mit.edu/6.004
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