Clocking and the Dynamic Discipline

2/19/98


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Table of Contents

Clocking and the Dynamic Discipline

Recap: Latches and Flip-Flops

Synchronous Sequential Circuit

It is time to worry about timing...

Edge-Triggered Flip-Flop Timing

Synchronous Circuit: Clocked Flip-Flop

Flip-Flop Clocking Rules

Hold Time Constraint for Flip-Flop

Transparent D-Latch Timing

Synchronous Circuit: Clocked Latch

Avoiding Races: Latch Clocking Rules

Clock Period Constraint for Latch

Clock Skew

Asynchronous Inputs = Trouble

Coordinates

Next Time: Finite State Machines

Author: Srinivas Devadas

Email: devadas@mit.edu

Home Page: http://cag-www.lcs.mit.edu/6.004

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