6.373 Lectures, Spring 1997

• Lecture-01: Overview
• Lecture-02: Logic Minimization
• Lecture-03: Heuristic Logic Minimization
• Lecture-04: Multilevel Logic Optimization - I
• Lecture-05: Multilevel Logic Optimization - II
• Lecture-06: Technology Mapping
• Lecture-07: Input Encoding
• Lecture-08: FSM Synthesis
• Lecture-09: FSM Decomposition
• Lecture-10: Retiming
• Lecture-11: Combinatorial Optimization Strategies
• Lecture-12: Power Estimation
• Lecture-13: Power Optimization
• Lecture-14: Test Generation
• Lecture-15: Synthesis for Testability - I
• Lecture-16: Synthesis for Testability - II
• Lecture-17: Two-Level Logic Verification
• Lecture-18: Multilevel Logic Verification
• Lecture-19: Sequential Logic Verification
• Lecture-20: Timing Analysis
• Lecture-21: Design Verification - I
• Lecture-22: Design Verification - II
• Lecture-23: RTL and Behavioral Synthesis
• Lecture-24: Embedded System Design
• Lecture-25: Processor Design and Retargetable Compilation
• Lecture-26: What's Next in CAD?