Test Generation and Synthesis for Testability

S. Devadas and K. Keutzer, "An Algorithmic Approach to Optimizing Fault Coverage for BIST Logic Synthesis", Proceedings of the International Test Conference, October 1998.

S. Devadas and K. Keutzer, "Synthesis of Robust Delay-Fault Testable Circuits: Theory ", IEEE Transactions on Computer-Aided Design, pp. 87-101, January 1992.

S. Devadas and K. Keutzer, "Synthesis of Robust Delay-Fault Testable Circuits: Practice", IEEE Transactions on Computer-Aided Design, pp. 277-300, March 1992.