The Four Instruction Computer (FIC)

A CPU Design in 65 Lines of Verilog!

The Four Instruction Computer (FIC) was my final project for the compilers class at Princeton, COS 320 (spring 2008, then taught by Andrew Appel). It included:

• A CPU design, specified in Verilog. It would run on a Spartan-3 Starter Kit, like previous projects. The native instruction set consists of ADD, NOR, JCZ, and SAVE. Here's the block diagram and state transition table (may be slightly out of date with the final version embodied in the Verilog implementation—I can't remember).
• An assembler, written in C.
• An emulator, written in C. Note that the emulator simulates the exact logic embodied in the Verilog CPU definition, down to every single clock cycle (see the onecycle function).
• A virtual machine for emulating a more flexible, stack-based instruction set (inspired by MuP21 and friends). The emulated instruction set consists of JMP, JZ, CALL, CALLA, RET, PUSH, POP, DROP, LIT, ADD, SUB, MULT, EQ, LT, LOAD, SAVE, ALLOC, and IOEX. The source code for the virtual machine is assembled by first running it through M4, a standard UNIX macro processor.
• A backend for the COS 230 compiler (written in SML) that allowed code to be generated for the emulated instruction set using a high-level functional language. Source code here (only includes the FIC-specific parts of the compiler).

In the end, the compiler/virtual machine/hardware stack passed the complete set of automated tests designed collectively by the entire class. You can read the complete readme for the project here.