Ph.D. Candidate in Electrical Engineering and Computer Science
(GPA: 5.0/5.0) (Expected graduation date: 01/2017)

M.S. in Electrical Engineering and Computer Science (GPA: 5.0/5.0)

B.S. in Electrical Engineering (GPA: 4.0/4.0) (Class Rank: 1/224)

Research Intern, Mentored by Kermin Fleming and Michael Adler

• Developed algorithms and microarchitectures for partitioning FPGA-based cache networks to efficiently utilize the bandwidth of multiple board-level memories on modern FPGAs
• Designed a resources-aware compiler to automate program-optimized cache network partitioning

Research Intern, Mentored by Michael Adler and Joel Emer

• Examined prefetching as a means of improving the performance of the LEAP memory, an automatically synthesized FPGA memory abstraction
• Designed an FPGA-optimized microarchitecture for prefetching, which is tuned for the behavior of typical FPGA applications

Advised by Prof. Joel Emer and Prof. Srini Devadas

• Built program introspection tools to analyze FPGA applications' runtime memory access characteristics
• Developed optimization algorithms to construct cache networks that minimize network latency impact and achieve good load balance cross multiple board-level memories
• Designed a complier (in Python) that automatically customizes the memory system tailored for a given application based on program introspection results and available hardware resources
• Extended optimized memory services to high-level-synthesis (HLS) applications

Advised by Prof. Joel Emer and Prof. Srini Devadas

• Built a shared memory infrastructure for FPGA-based parallel programming algorithms
• Developed a shared-memory service that automatically manages multiple coherent caches and coherence domains across multiple FPGAs
• Built novel lock and barrier primitives outside of shared memory to leverage native FPGA communication capabilities

Advised by Prof. Nickolai Zeldovich and Prof. Srini Devadas

• Built an authenticated cloud storage system that efficiently ensures data integrity and freshness by attaching a small piece of high-performance trusted hardware to an untrusted server
• Designed security mechanisms for trusted storage, including memory authentication, system state protection against power loss, access control, and crash recovery
• Implemented the trusted hardware on FPGA (using Verilog), the untrusted server on a Linux machine (using C++ and Ruby), and a client model with filesystem support
• Partitioned the functionality across software and hardware to improve system performance

Advised by Prof. Liang-Gee Chen

• Proposed a hybrid color calibration algorithm for the virtual view synthesis and tested it using C++
• Conducted hardware architectural analysis and implemented the hardware-oriented algorithm (in Verilog)
• Assisted a tape-out work for the view-synthesis chip in 45nm technology

Teaching Assistant

• Co-led weekly tutorials to walk through problem set questions and clarify concepts from lectures
• Assisted students with laboratory exercises modeling different microarchitectures with Intel Pin tool
• Created and graded monthly quizzes