\HeadingLevelC{Page Walker Input}
\label{sec:pmh_walker_input}

Sanctum's per-enclave page tables require an enclave page table base register
\texttt{eptbr} that stores the physical address of the currently running
enclave's page tables, and has similar semantics to the page table base
register \texttt{ptbr} pointing to the operating system-managed page tables.
These registers may only be accessed by the Sanctum security monitor, which
provides an API call for the OS to modify \texttt{ptbr}, and ensures that
\texttt{eptbr} always points to the current enclave's page tables.

The circuitry handling TLB misses switches between \texttt{ptbr} and
\texttt{eptbr} based on two registers that indicate the current enclave's
EVRANGE, namely \texttt{evbase} (enclave virtual address space base) and
\texttt{evmask} (enclave virtual address space mask).
When a TLB miss occurs, the circuit in Figure~\ref{fig:page_walker_input}
selects the appropriate page table base by ANDing the faulting virtual address
with the mask register and comparing the output against the base register.
Depending on the comparison result, either \texttt{eptbr} or \texttt{ptbr} is
forwarded to the page walker as the page table base address.

\begin{figure}[htb]
  \center{\includegraphics[width=65mm]{figures/page_walker_input.pdf}}
  \caption{
    Page walker input for per-enclave page tables.
  }
  \label{fig:page_walker_input}
%\EndFigure
\end{figure}

% NOTE: this is tallied in the evaluation section
In addition to the page table base registers, Sanctum uses 3 more pairs of
registers that will be described in the next section. On a 64-bit RISC-V
computer, the modified FSM input requires 5 extra 52-bit registers (the
bottom 12 bits in a 64-bit page-aligned address will always be zero), 52 AND
gates, a 52-bit wide equality comparator (52 XNOR gates and 51 AND gates),
and 208 ($52 \times 4$) 2-bit MUXes.
