Date: Sun, 5 Nov 95 16:36:02 PSTI design electronics for a living. In my latest project, almost the entire design is simulated in SCM, translated to VHDL by SCM, and tested from SCM. I have also written the low level part of an NT device driver in SCM which I translate to C using my old compiler, now called schlep.
From: ...
From: jaffer (Aubrey Jaffer)I work for a small EDA software firm specializing in custom IC verification tools. I use lisp and scheme occasionally, and wonder, out of curiosity, what sort of simulator do you have that's written in scheme? I was trying to look for applications that would allow me to use more scheme, but never thought of simulators that have been considered to be memory and cpu resource intensive.I have spent most of this year running millions of cycles of simulation of custom integrated circuits entirely in SCM. The simulations routinely run on several different platforms and take hours.
This project is a decompression chip which maintains up to 40 parallel decompression streams which accept 7 coding regimes. There are several synchronous subsystems, each of which is simulated using a SCM file which uses defmacros from a file called "simsynch.scm". "Simsynch.scm" creates a database of logical and numerical expressions for each synchronous system. For simulation, SIMSYNCH creates scheme procedures (programs which can be compiled to C by Hobbit). These programs output mixed state and timing diagrams (such as produced by logic analyzers) or other output. Communication between the synchronous subsystems is time sliced using continuations.
This is the most complicated electronic design I have seen through to completion. In spite of the complexity, having the entire design accessible through the SCM interface has meant that almost all of my debugging has been done seated comfortably in front of the computer, rather than hunched over straining to see (with my ailing vision) and hold tiny probes on 25mil (.65mm) pitch surface mount leads.
Many of the tests used to debug the simulated design are collected into a diagnostic module which is run when the board is initialized.
The physical realization.
(synch:set! tile-y0 (and (not loading-bases) (xor y-incr tile-y0))) (synch:set! tile-y1 (and (not loading-bases) (xor (and y-incr tile-y0) tile-y1))) (synch:set! tile-y2 (and (not loading-bases) (xor (and y-incr tile-y0 tile-y1) tile-y2))) (synch:set! tile-y3 (and (not loading-bases) (xor (and y-incr tile-y0 tile-y1 tile-y2) tile-y3))) (synch:set! tile-y4 (and (not loading-bases) (xor (and y-incr tile-y0 tile-y1 tile-y2 tile-y3) tile-y4))) (synch:set! tile-y5 (and (not loading-bases) (xor (and y-incr tile-y0 tile-y1 tile-y2 tile-y3 tile-y4) tile-y5)))
831
S T A R R R D D D D L D T D D D P T D
T I M D D D L L L L O Q P Q C C D P C
A L R F M F O R W Y O - S - D C A D D
T E E I T L E E E - K O Z A - - T A -
E - N F # # # F - E / D H V A T P
X O U S N S V L L V O W
# L F D D K E
N
tw 40 | | | | | | | 14 | | 22 | | | | | |
td 40 | | | | | | | 14 | | 11 | | | | | |
td 40 | | | | | | | 14 | | 11 | | | | | |
td 40 | | | | | | | 14 | | 11 | | | | | |
td 40 | | | | | | | 14 | | 11 | | | | | |
td 40 | | | | | | | 14 | | 44 | | | | | |
td 00 | | | | | | | 14 | | 44 | | | | | | ::
td 01 | | | | | | | 15 | | 44 | | | | | |
td 01 | | | | | | | 15 | | 44 | | | | | |
td 01 | | | | | | | 15 | | 44 | | | | | | ::
td 02 | | | | | | | 16 | | 44 | | | | | | ::
td 03 | | | | | | | 17 | | 44 | | | | | | ::
td 04 | | | | | | | 18 | | 44 | | | | | | ::
td 05 | | | | | | | 19 | | 44 | | | | | | ::
td 06 | | | | | | | 1a | | 44 | | | | | | e-b ::
td 07 | | | | | | | 1b | | ?? | | | | | | ::
td 00 | | | | | | | 1c | | ?? | | | | | |
td 00 | | | | | | | 1c | | ?? | | | | | |
td 00 | | | | | | | 1c | | ?? | | | | | | ::
td 01 | | | | | | | 1d | | ?? | | | | | |
ta 01 | | | | | | | 1d | | 11 | | | | | | ptrd #x1c270
tg 01 | | | | | | | 1d | | aA | | | | | | ptrd #x1c270
tg 00 | | | | | | | 1e | | aA | | | | | |
tg 00 | | | | | | | 1e | | -- | | | | | |
tg 00 | | | | | | | 1e | | tt | | | | | | * 1/2w Z 2Y Tile ::
dp 40 | | | | | | | 1e | | aa | | | | | | ptwr #x1c6e4
dp 40 | | | | | | | 1e | | aa | | | | | | ::
dp 40 | | | | | | | 1d | | 00 | | | | | |
dp 40 | | | | | | | 1d | | 00 | | | | | |
dp 40 | | | | | | | 1d | | 00 | | | | | |
dp 40 | | | | | | | 1d | | 00 | | | | | |
dp 40 | | | | | | | 1d | | 44 | | | | | | ::
dp 40 | | | | | | | 1e | | 44 | | | | | | 2xlit 14
dp 41 | | | | | | | 1e | | 33 | | | | | |
dp 42 | | | | | | | 1e | | 33 | | | | | |
dp 43 | | | | | | | 1e | | 22 | | | | | |
dp 44 | | | | | | | 1e | | 22 | | | | | |
dp 45 | | | | | | | 1e | | 11 | | | | | |
dp 46 | | | | | | | 1e | | 11 | | | | | |
dp 46 | | | | | | | 1e | | 00 | | | | | |
dp 46 | | | | | | | 1e | | 44 | | | | | | ::
dp 47 | | | | | | | 1f | | 44 | | | | | |
dp 48 | | | | | | | 1f | | 44 | | | | | |
dp 49 | | | | | | | 1f | | 33 | | | | | |
dp 4a | | | | | | | 1f | | 33 | | | | | |
dp 4b | | | | | | | 1f | | 22 | | | | | |
dp 4c | | | | | | | 1f | | 22 | | | | | |
dp 4d | | | | | | | 1f | | 11 | | | | | |
dp 4e | | | | | | | 1f | | 11 | | | | | |
dp 4e | | | | | | | 1f | | 00 | | | | | |
Copyright 1995 Aubrey Jaffer
|
I am a guest and not a member of the MIT Computer Science and Artificial Intelligence Laboratory.
My actions and comments do not reflect in any way on MIT. | ||
| SCM for Engineering | ||
| agj @ alum.mit.edu | Go Figure! | |