;			 loading SIMSYNCH 1b7
 Opening simulation dump file "fifo8-spew.dat"
 00 |  ?? |  |  00 00  | | 
   1
 C  R  D  W  R  D  W  E  F
 Y  E  I  R  D  O  R  M  U
 C  S  N  -  -  U  -  P  L
 L  E     E  E  T  C  T  L
 E  T     N  N     N  Y   
                   T      

 01 |  ?? |  |  00 00  | | 
 02 |  ?? |  |  00 00  | | 
 03 |  ?? |  |  00 00  | | 
 04 |  ?? |  |  00 00  | | 
 05 |  0f  | |  00 00  | | 
 06 |  0e  | |  00 01 |  | 
 07 |  0d  | |  00 02 |  | 
 08 |  0c  | |  00 03 |  | 
 09 |  0b  | |  00 04 |  | 
 0a |  0a  | |  00 05 |  | 
 0b |  09  | |  00 06 |  | 
 0c |  08  | |  00 07 |  | 
 0d |  07 |  |  00 08 |   |
 0e |  06 |  |  00 08 |   |
 0f |  05 |  |  00 08 |   |
 10 |  04 |  |  00 08 |   |
 11 |  03 |  |  00 08 |   |
 12 |  02 |  |  00 08 |   |
 13 |  ?? |  |  00 08 |   |
 14 |  ?? |  |  00 08 |   |
 15 |  ?? |  |  00 08 |   |
 16 |  ?? |  |  00 08 |   |
 17 |  ?? |  |  00 08 |   |
 18 |  ?? |  |  00 08 |   |
 19 |  ?? |   | 00 08 |   |
 1a |  ?? |   | 0f 07 |  | 
 1b |  ?? |   | 0e 06 |  | 
 1c |  ?? |   | 0d 05 |  | 
 1d |  ?? |   | 0c 04 |  | 
 1e |  ?? |   | 0b 03 |  | 
 1f |  ?? |   | 0a 02 |  | 
 20 |  ?? |   | 09 01 |  | 
 21 |  ?? |  |  08 00  | | 
 22 |  ?? |  |  08 00  | | 
 23 |  ?? |  |  08 00  | | 
 24 |  ?? |  |  08 00  | | 
 25 |  ?? |  |  08 00  | | 
 26 |  ?? |  |  08 00  | | 
 27 |  ?? |  |  08 00  | | 
;; State dump for test fifo
(dump:vhdl
  "test-spew.dat"
  fifo
  60.0e6
  wr-clk
  reset
  wr-en
  rd-en
  rd-clk
  din[7:0]
  wr-count[3:0]
  full
  empty
  dout[7:0])

translating test for ptag fifo
generating test_fifo.vhd
generating test_stim.vhd
instantiate test fifo