This is the original form of simsynch. It grew over time, so it is poorly organized. But I have a lot of modules written this way.
Adds the scheme expression expr to the body of the *block* simulator. Check expressions are evaluated once per clock cycle of their block while the block's reset is deasserted.
Check expressions are evaluated in the order in which they are defined by
synch:defcheck
.
Synch:pre is a macro that saves typing.
synch:pre
retrieves the next-function expression of signal. Usingsynch:pre
has the same effect of inserting the second argument of thesynch:set!
specifying signal.
The following defmacros treat their pin-name, signal,
name argument specially. If the symbol contains a colon
(‘:’), the part before the colon is the ptag and the part after is
the signal name. If the colon is the last character, then the name is
#f
, which is used for signals which do not connect to pins. If
the part after the colon is a number, then the (pin's) name is that
number.
synch:set!
, synch:set/reset!
, and synch:pre
do not
accept ‘:’ encoded signal-names.
If the pin-name argument is ?
(question-mark), this
indicates that the fitter should assign a pin(s) for this signal. The
assignments for bussed signals can be a range of pin names
(eg. ‘addr[12..0]’) or a parenthesized list of pin names or
numbers (eg. ‘(34 25 61 12’).
Defines name to be a signal of type
macro
whose value is expression. name will translate to a macro in the hardware description language which replaces name with expression.
Identifies pin-name (or name if single argument) of chip ptag with an already defined signal name.
synch:defshare
is used when connecting inputs in one package to outputs on another. These outputs need not originate from chips which are generated; they may also come from hidden models.
Defines a pin used only for input. expression is computed as a hidden macro.
Defines a pin used only for input, but whose signal is delayed by one clock cycle.
Defines a synchronous signal and pin.
synch:define
defines all of the informationsynch:define-pin
andsynch:define-signal
do. If next-function is absent, then it must be supplied by use ofsynch:set!
.output-enable is a boolean valued expression which controls whether the signal drives the pin(s). pin is
#f
or a symbol which names the signal at the pin. Note that the values of pin will necessarily match the values of signal only while output-enable is#t
. signal and pin can be the same symbol if you have no need to access the (possibly undriven) signal.(synch:define #f XP:tl-raw #t #f #f)defines an internal signal with initial value
#t
.(synch:define 36 XP:dloe- #t dloe- #t)defines an output named dloe-.
(synch:define (34 33 32) XP:stpsz-out[2..0] #.tpsz-tag stpsz[2..0] dloe-) (synch:defmacro HID:stpsz[2..0] (cond (dloe- stpsz-out[2..0]) ((not last-dloe-) dly:-fo-tag-reg) (else -1)))defines bussed pins stpsz[2..0] sometimes driven by the vectorized signal stpsz-out[2..0], which is always available to the design. HID:stpsz[2..0] emulates the signals at the pins which can be driven from various sources.
reset-state is the value held by this signal while reset-name for this block is asserted. reset-state should be a boolean for single signals and an integer for vectorized signals. If reset-name is a list with first element ‘synchronous’, then the reset state is unspecified if no clock is present during reset; and the second element of reset-name otherwise. If reset-name is ‘*xxxx*’, then the reset state is unspecified if no clock is present during reset; next-function otherwise.
The scheme expression next-function determines the values for signal while the block's reset is deasserted.