module re_top(PI8, PI9A, PIB, RDYI8, RDYI9A, RDYIB, YI8, YI9, YIA, YIB,
	      PO8, PO9A, POB, RDYO8, RDYO9A, RDYOB, YO8, YO9, YOA, YOB,
	      RE_RAW_CLK, PI_RE_RAW_CLKO, PI_RE_RAW_CLKI, GLOBAL_RESET,
	      LED_BUS, TEST_D_BUS, PI_RIGHT_LOCK);

   input	 RE_RAW_CLK;
   input	 GLOBAL_RESET;

   input	 PI_RE_RAW_CLKI;
   output	 PI_RE_RAW_CLKO;
    
   output [7:0]	 LED_BUS;
   output [47:0] TEST_D_BUS;

   output	 PI_RIGHT_LOCK;
   
   output [31:0] PI8;
   output [31:0] PI9A;
   output [31:0] PIB;
   
   input [31:0]	 PO8;
   input [31:0]	 PO9A;
   input [31:0]	 POB;
   
   reg [31:0]	 PO8_reg;
   reg [31:0]	 PO9A_reg;
   reg [31:0]	 POB_reg;

   output [1:0]	 RDYI8;
   output [2:0]	 RDYI9A;
   output [1:0]	 RDYIB;
   
   input [1:0]	 RDYO8;
   input [2:0]	 RDYO9A;
   input [1:0]	 RDYOB;

   reg [1:0]	 RDYO8_reg;
   reg [2:0]	 RDYO9A_reg;
   reg [1:0]	 RDYOB_reg;

   output [2:0]	 YI8;
   output [2:0]	 YI9;
   output [2:0]	 YIA;
   output [2:0]	 YIB;

   input [2:0]	 YO8;
   input [2:0]	 YO9;
   input [2:0]	 YOA;
   input [2:0]	 YOB;

   reg [2:0]	 YO8_reg;
   reg [2:0]	 YO9_reg;
   reg [2:0]	 YOA_reg;
   reg [2:0]	 YOB_reg;

   reg [7:0]	 error_count;
   reg [47:0]	 debug_data;
   
   // Make sure we are not sending any data to Raw
   assign PI8 = 32'd0;
   assign PI9A = 32'd0;
   assign PIB = 32'd0;

   assign RDYI8 = 2'd0;
   assign RDYI9A = 3'd0;
   assign RDYIB = 2'd0;

   assign YI8 = 3'd0;
   assign YI9 = 3'd0;
   assign YIA = 3'd0;
   assign YIB = 3'd0;

   assign LED_BUS = error_count;
   assign TEST_D_BUS = debug_data;
      
   wire	gnd = 1'b0;
   wire	RAW_CLK;
   wire	locked1, locked2;
   wire	Reset = GLOBAL_RESET | ~locked1;

   // Bring in and deskew the Raw clock
   IBUFG_HSTL_I ibufg0 (.I(RE_RAW_CLK), .O(RE_RAW_CLK_tmp));

   DCM dll0(.CLKIN(RE_RAW_CLK_tmp), .CLKFB(RAW_CLK), .RST(GLOBAL_RESET), 
            .DSSEN(gnd), .PSINCDEC(gnd), .PSEN(gnd), .PSCLK(),
	    .CLK0(), .CLK90(), .CLK180(), .CLK270(),
            .CLK2X(RAW_CLK_tmp), .CLK2X180(), .CLKDV(), .CLKFX(), .CLKFX180(), 
            .LOCKED(locked1), .STATUS(), .PSDONE());

   BUFG rawClkBufG(.I(RAW_CLK_tmp), .O(RAW_CLK));

   // Send copy of the Raw clock to PI and use DCM to make
   //  sure it arrives there at the same time we get it.
   DCM dll1(.CLKIN(RE_RAW_CLK_tmp), .CLKFB(RAW_CLK_fb_PI), .RST(GLOBAL_RESET),
	    .DSSEN(gnd), .PSINCDEC(gnd), .PSEN(gnd), .PSCLK(),
	    .CLK0(PI_RE_RAW_CLKO), .CLK90(), .CLK180(), .CLK270(),
            .CLK2X(), .CLK2X180(), .CLKDV(), .CLKFX(), .CLKFX180(),
            .LOCKED(locked2), .STATUS(), .PSDONE());

   assign PI_RIGHT_LOCK = locked2;
   
   IBUFG pciFbIBufg(.I(PI_RE_RAW_CLKI),.O(RAW_CLK_fb_PI));
      
   // Capture data from Raw, even though we don't use it
   always @(posedge RAW_CLK or posedge Reset) begin
      if (Reset) begin
	 RDYO8_reg <= 2'b00;
	 RDYO9A_reg <= 3'b000;
	 RDYOB_reg <= 3'b00;
	 
	 YO8_reg <= 3'b000;
	 YO9_reg <= 3'b000;
	 YOA_reg <= 3'b000;
	 YOB_reg <= 3'b000;
	 
	 error_count <= 8'b11111111;
	 debug_data <= 48'd0;	 
      end // if (Reset)
      else begin
	 RDYO8_reg <= RDYO8;
	 RDYO9A_reg <= RDYO9A;
	 RDYOB_reg <= RDYOB;
	 
	 YO8_reg <= YO8;
	 YO9_reg <= YO9;
	 YOA_reg <= YOA;
	 YOB_reg <= YOB;

	 PO8_reg <= PO8;
	 PO9A_reg <= PO9A;
 	 POB_reg <= POB;

	 if (((YO8_reg | YO9_reg | YOA_reg | YOB_reg) != 3'b000) |
	     ((RDYO8_reg | RDYOB_reg) != 3'b00) |
	     (RDYO9A_reg != 3'b000))
	    error_count <= {error_count[6:0], 1'b0};

	 /*
	 debug_data[5:0]   <= {YO8_reg,(PO8_reg != 32'd0),RDYO8_reg};
	 debug_data[15:6]  <= {YOA_reg,YO9_reg,(PO9A_reg != 32'd0),RDYO9A_reg};
	 debug_data[21:16] <= {YOB_reg,(POB_reg != 32'd0),RDYOB_reg};
	 */
	 debug_data[47:16] <= PO8_reg;
	 debug_data[6:0]   <= {RDYOB_reg, RDYO9A_reg, RDYO8_reg};
	 debug_data[15:7]  <= {7'd0, (POB_reg != 32'd0), (PO9A_reg != 32'd0)};
	 
      end // else: !if(Reset)
   end // always @ (posedge RAW_CLK or posedge Reset)
endmodule