LIB_OPTS = -y /home/tools/ibm_sa27e/current/synthesis/synopsys_dw/src_ver \
           -y /home/tools/ibm_sa27e/current/verilog \
           -y ../../../../../..//ibm_sa27e/verilog_wrapper \
           -y ../../../../../..//ibm_sa27e/sim \
           -y ../../../../../..//sim \
           -y ../../../../../..//src/components \
           -y ../../../../../..//src/chip \
           -y ../../../../../..//src/chip/iomux \
           -y ../../../../../..//src/chip/tile \
           -y ../../../../../..//src/chip/tile/switch/common \
           -y ../../../../../..//src/chip/tile/switch/dynamic \
           -y ../../../../../..//src/chip/tile/switch/static \
           -y ../../../../../..//src/chip/tile/proc \
           -y ../../../../../..//src/chip/tile/proc/dcache2 \
           -y ../../../../../..//src/chip/tile/proc/divide \
           -y ../../../../../..//src/chip/tile/proc/fp \
           -y ../../../../../..//src/chip/tile/proc/mainpipe \
           -y ../../../../../..//src/chip/tile/proc/multiply/mult28 \
           +libext+.v \
           +incdir+.. \
           +incdir+../../../../../../src/components \
           +incdir+../../../../../../src/chip/tile/proc/mainpipe \
           +incdir+../../../../../../src/chip/tile/switch/static \
	   +incdir+/home/tools/ibm_sa27e/current/synthesis/synopsys_dw/src_ver

PLI_DIR  = ../../../../../../testing/get_stim
PLI_OPTS = -P $(PLI_DIR)/get_stim.tab $(PLI_DIR)/get_stim.c +acc \
	   -CC -I/home/tools/synopsys/vcs/sun_sparc_solaris_5.4/lib

vcs:
	vcs -Mupdate -PP +define+USEVPD+ -f switch.files $(LIB_OPTS)

xvcs:
	vcs -Mupdate -RI -line -f switch.files $(LIB_OPTS) $(PLI_OPTS)

dump: 
	simv $@ +dump

wave:
	vcs -RPP +vpdfile+vcdplus.vpd

clean:
	$(RM) -r csrc simv.daidir vcs.key simv

xl:
	/home/cad/cadence/IC/current/tools.sun4v/bin/verilog -f switch.files