A Reconfigurable Architecture for Load-Balanced Rendering
Jiawen Chen1,
Michael I. Gordon1,
William Thies1,
Matthias Zwicker1,
Kari Pulli2,1,
Frédo Durand1
1Massachusetts Institute of Technology, Computer Science and Artificial Intelligence Laboratory
2Nokia Research Center
Commodity graphics hardware has become increasingly programmable over
the last few years but has been limited to fixed resource allocation.
These architectures handle some workloads well, others poorly;
load-balancing to maximize graphics hardware performance has become a
critical issue. In this paper, we explore one solution to this
problem using compile-time resource allocation. For our experiments,
we implement a graphics pipeline on Raw, a tile-based multicore
processor. We express both the full graphics pipeline and the shaders
using StreamIt, a high-level language based on the stream programming
model. The programmer specifies the number of tiles per pipeline
stage, and the StreamIt compiler maps the computation to the Raw
architecture.
We evaluate our reconfigurable architecture using a mix of common
rendering tasks with different workloads and improve throughput by
55-157% over a static allocation. Although our
early prototype cannot compete in performance against commercial
state-of-the-art graphics processors, we believe that this paper
describes an important first step in addressing the load-balancing
challenge.