I am on the academic job market.
I am a final-year PhD student at the Massachusetts Institute of Technology, where I am advised by Professor Daniel Sanchez in the Computer Science and Artificial Intelligence Laboratory. My work on parallel computer systems aims to scale hard-to-parallelize applications through new programming models and multicore architectures. I earned an MASc while working with Professor Greg Steffan and a BASc in Engineering Science from the University of Toronto. Before attending MIT, I was a software engineer at AeroFS, working on distributed file sharing.
2018 SAM: optimizing multithreaded cores for speculative parallelism. In Proc. of the 26th international conference on Parallel Architectures and Compilation Techniques (PACT-26). September 2017. [text] [doi] [slides] PACT
2017 Fractal: an execution model for fine-grain nested speculative parallelism. In Proc. of the 44th ACM/IEEE International Symposium on Computer Architecture (ISCA-44). June 2017. [text] [slides] [press: MIT News] ISCA
2017 Data-centric execution of speculative parallel programs. In Proc. of the 49th IEEE/ACM international symposium on Microarchitecture (MICRO-49). October 2016. [text] [doi] [slides] MICRO
2016 Unlocking ordered parallelism with the Swarm architecture. IEEE Micro's Top Picks from the Computer Architecture Conferences, 36(3). May/June 2016. [text] [doi] [press: MIT News, EEJournal, HPCwire] IEEE
2016 A scalable architecture for ordered parallelism. In Proc. of the 48th IEEE/ACM international symposium on Microarchitecture (MICRO-48). December 2015. [text] [slides] MICRO
2015 Understanding and improving Bloom filter configuration for lazy address-set disambiguation. MASc Thesis, University of Toronto. 2011. [text] [slides] MASc
Thesis Application-specific signatures for transactional memory in soft processors. ACM Transactions on Reconfigurable Technology and Systems, 4(3). August 2011. [text] ACM
2011 Understanding Bloom filter intersection for lazy address-set disambiguation. In Proc. of the 23rd ACM Symposium on Parallelism in Algorithms and Architectures (SPAA). June 2011. [text] [slides] SPAA
2011 Application-specific signatures for transactional memory in soft processors. In Proc. of the 6th international symposium on Applied Reconfigurable Computing (ARC). March 2010. [doi] ARC