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PEER-REVIEWED JOURNALS 2018 [J10] L. Bu, M. Karpovsky and M. A. Kinsy: “Bulwark: Securing Implantable Medical Devices Communication Channels”. In the Elsevier Journal of Computers and Security (Computers & Security), 2018.[PDF] [bib] [J9] L. Bu, M. Karpovsky and M. A. Kinsy: “Design of Reliable Storage and Compute Systems with Lightweight Group Testing Based Non-Binary Error Correction Codes”. In the Institution of Engineering and Technology (IET), - Computers and Digital Techniques, 2018.[PDF] [bib] [J8] T. Yang, Y. Wei, Z. Tu, H. Zeng, M. A. Kinsy, N. Zheng and P. Ren: “Design Space Exploration of Neural Network Activation Function Circuits”. In the Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2018.[PDF] [bib] [J7] L. Bu, J. Dofe, Q. Yu and M. A. Kinsy: “SRASA: A Generalized Theoretical Framework for Security and Reliability Analysis in Computing Systems”. Journal of Hardware and Systems Security (HaSS), 2018.[PDF] [bib] [J6] S. M. Sebt, A. Patooghy, H. Beitollahi and M. A. Kinsy: “Circuit Enclaves Susceptible to Hardware Trojans Insertion at Gate-Level Designs”. In the Institution of Engineering and Technology (IET), - Computers and Digital Techniques, 2018.[PDF] [bib] [J5] L. Bu, M. Isakov, and M. A. Kinsy: “A Secure and Robust Scheme for Sharing Confidential Information in IoT Systems”. In the Elsevier Journal for Ad Hoc Networks, (Ad Hoc Networks), 2018.[PDF] [bib] [J4] M. A. Kinsy, L. Bu, M. Isakov and M. Mark: “Designing Secure Heterogeneous Multicore Systems from Untrusted Components”. Cryptography, vol. 2, iss. 3, no. 12, 2018.[PDF] [bib] 2016 [J3] P. Ren, M. Kinsy, and N. Zheng: “Fault-Aware Load-Balancing Routing for 2D-Mesh and Torus On-Chip Network Topologies.” In the Transactions on Computers (TC), March 2016.[PDF] [bib] [J2] P. Ren, X. Ren, S. Sane, M. Kinsy, and N. Zheng: “Deadlock-Free and Connectivity- Guaranteed Methodology for Achieving Fault-tolerance in On-chip Networks.” In the Transactions on Computers (TC), February 2016.[PDF] [bib] 2013 [J1] M. Kinsy, M. H. Cho, T. Wen, M. Lis , G. E. Suh, M. Dijk, and S. Devadas: “Optimal and Heuristic Application-Aware Oblivious Routing.” In the Transactions on Computers (TC), January 2013.[PDF] [bib] PEER-REVIEWED CONFERENCES 2018 [C37] A. Ehret, M. Isakov and M. A. Kinsy: “Towards a Generalized Reconfigurable Agent Based Architecture: Stock Market Simulation Acceleration”, International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2018.[PDF] [bib] [C36] M. Isakov, L. Bu, H. Cheng, and M. A. Kinsy: “Preventing Neural Network Model Exfiltration in Machine Learning Hardware Accelerators”. In the 2018 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), 2018.[PDF] [bib] [C35] M. Isakov and M. A. Kinsy: “NoSync: Particle Swarm Inspired Distributed DNN Training”. In the 27th International Conference on Artificial Neural Networks (ICANN), 2018.[PDF] [bib] [C34] L. Bu, H. Cheng, and M. A. Kinsy: “Fast Dynamic Device Authentication Based on Lorenz Chaotic Systems”. In 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), October 8-10, 2018.[PDF] [bib] [C33] M. Isakov, A. Ehret and M. Kinsy: “Chameleon: A Generalized Reconfigurable Open-Source Architecture for Deep Neural Network Training”. In the 2018 IEEE High Performance Extreme Computing Conference (HPEC), 2018.[PDF] [bib] [C32] L. Bu, H. Cheng, and M. Kinsy: “Adaptive and Dynamic Device Authentication Based on Lorenz Chaotic Systems”. In 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) Aug 2018.[PDF] [bib] [C31] L. Bu and M. Kinsy: “Weighted Group Decision Making Using Multi-identity Physical Unclonable Functions”. In the International conference on Field Programmable Logic and Applications (FPL), August 2018.[PDF] [bib] [C30] M. Isakov, A. Ehret and M. Kinsy: “ClosNets: Batchless DNN Training with On-Chip A Priori Sparse Neural Topologies”. In the International conference on Field Programmable Logic and Applications (FPL), August 2018.[PDF] [bib] [C29] L. Bu, M. Mark and M. Kinsy: “A Short Survey at the Intersection of Reliability and Security in Processor Architecture Designs”. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2018.[PDF] [bib] [C28] S. Kashi, A. Patooghy, D. Rahmati, M. Fazeli and M. A. Kinsy: “Application Specific Networks-on-Chip Synthesis: An Energy Efficient Approach”. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2018.[PDF] [bib] [C27] E. Aerabi, A. Patooghy, H. Rezaei, M. Mark, M. Fazeli and M. Kinsy: “Mystic: Mystifying IP Cores Using an Always-ON FSM Obfuscation Method”. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2018.[PDF] [bib] [C26] A. Ehret, P. Jamieson and M. A. Kinsy: “Scalable Open-Source Reconfigurable Architecture for Bacterial Quorum Sensing Simulations”, International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), June 2018.[PDF] [bib] [C25] L. Bu and M. Kinsy: “Hardening AES Hardware Implementations Against Fault and Error Inject Attacks”. In the ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2018.[PDF] [bib] 2017 [C24] K. Soleimani, A. Patooghy, N. Soltani, L. Bu, M. A. Kinsy: “Crosstalk Free Coding Systems to Protect NoC Channels Against Crosstalk Faults.” In 2017 IEEE 35th International Conference on Computer Design (ICCD), November 2017.[PDF] [bib] [C23] J. R. Doppa, R. G. Kim, M. Isakov, M. A. Kinsy, H. Kwon and T. Krishna: “Adaptive Manycore Architectures for Big Data Computing.” In the International Symposium on Networks-on-Chip (NOCS), October 2017.[PDF] [bib] [C22] L. Bu, H. D. Nguyen, and M. A. Kinsy: “RASSS: A perfidy-aware protocol for designing trustworthy distributed systems.” In the 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), October 2017.[PDF] [bib] Best Student Paper Award and Best Paper Nominee [C21] E. Taheri, M. Isakov, A. Patooghy, and M. Kinsy: “Advertiser Elevator: a Fault Tolerant Routing Algorithm for Partially Connected 3D Network-on-Chips.” 60th International Midwest Symposium on Circuits and Systems (MWSCAS) Aug 2017.[PDF] [bib] [C20] H. Hosseinzadeh, M. Isakov, M. Darabi, A. Patooghy, and M. Kinsy: “Janus: An uncertain cache architecture to cope with side channel attacks.” 60th International Midwest Symposium on Circuits and Systems (MWSCAS) Aug 2017.[PDF] [bib] The Myril B. Reed Best Paper Award [C19] M. Kinsy, S. Khadka and M. Isakov: “PreNoc: Neural Network based Predictive Routing for Network-on-Chip Architectures.” in the 27th edition of the ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2017.[PDF] [bib] [C18] M. Kinsy, S. Khadka, M. Isakov and A. Farrukh: “Hermes: Secure Heterogeneous Multicore Architecture Design.” In the IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2017.[PDF] [bib] 2016 [C17] P. Ren, M. Kinsy, M. Zhu and N. Zheng: “Towards Connectivity-Guaranteed Power-gating Large-scale On-chip Networks.” The 7th International Green and Sustainable computing conference (IGSC), Nov 7-9, 2016.[PDF] [bib] 2015 [C16] J. Mohr and M. Kinsy: “Securitas: Multi-Tenant Secure Computer Architecture.” In the 40th Government Microcircuit Applications and Critical Technology Conference (GOMACTech-15), April, 2015.[PDF] [bib] 2014 [C15] M. Kinsy and S. Devadas: “Low-Overhead Hard Real-time Aware Interconnect Network Router.” In IEEE High Performance Extreme Computing (HPEC), September, 2014.[PDF] [bib] [C14] M. Kinsy and S. Devadas: “Algorithms for Scheduling Task-based Applications onto Heterogeneous Many-core Architectures.” In IEEE High Performance Extreme Computing (HPEC), September, 2014.[PDF] [bib] 2013 [C13] M. Kinsy, I. Celanovic, O. Khan, and S. Devadas: “MARTHA: Architecture for Control and Emulation of Power Electronics and Smart Grid Systems.” In IEEE International Conference on Design, Automation and Test in Europe (DATE), March, 2013.[PDF] [bib] [C12] M. Kinsy, M. Pellauer, and S. Devadas: “Heracles: A Tool for Fast RTL-Based Design Space Exploration of Multicore Processors.” In Proceedings of the 21st International Symposium on Field-Programmable Gate Arrays (FPGA), February 2013.[PDF] [bib] 2012 [C11] J. Poon, M. Kinsy, N. Pallo, S. Devadas, and I. Celanovic: “Hardware-in-the-loop testing for electric vehicle drive applications.” In Proceedings of the 27th Annual IEEE Applied Power Electronics Conference and Exposition (APEC), February 2012.[PDF] [bib] 2011 [C10] M. Kinsy, O. Khan, I. Celanovic, M. Dusan, N. Celanovic, and S. Devadas: “Time- Predictable Computer Architecture for Cyber-Physical Systems: Digital Emulation of Power Electronics Systems.” In Proceedings of the 32nd Real-Time Systems Symposium (RTSS), December 2011.[PDF] [bib] [C9] M. Kinsy, M. Pellauer, and S. Devadas: “Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System.” In Proceedings of the 21st International Conference on Field Programmable Logic and Applications (FPL), September 2011.[PDF] [bib] Tools and Open-Source Community Service Award [C8] M. Lis, K. S. Shim, M. H. Cho, C. Fletcher, M. Kinsy, I. Lebedev, O. Khan, and S. Devadas: “Brief Announcement: Distributed Shared Memory based on Computation Migration.” In Proceedings of the 23rd Symposium on Parallelism in Algorithms and Architectures (SPAA), June 2011.[PDF] [bib] [C7] M. Kinsy, D. Majstorovic, P. Haessig, J. Poon, N. Celanovic, I. Celanovic, and S. Devadas: “High-Speed Real-Time Digital Emulation for Hardware-in-the-Loop Testing of Power Electronics: A New Paradigm in the Field of Electronic Design Automation (EDA) for Power Electronics Systems.” In Proceedings of the 2011 International Exhibition and Conference for Power Electronics, Intelligent Motion, Power Quality (PCIM Europe), May 2011.[PDF] [bib] [C6] M. Pellauer, M. Adler, M. Kinsy, A. Parashar, and J. Emer: “HAsim: FPGA-based highdetail multicore simulation using time-division multiplexing.” In Proceedings of the 17th International Symposium on High Performance Computer Architecture (HPCA), February 2011.[PDF] [bib] 2009 [C5] M. H. Cho, M. Lis, K. S. Shim, M. Kinsy, T. Wen, and S. Devadas: “Oblivious Routing in On-Chip Bandwidth-Adaptive Networks.” In Proceedings of the Parallel Architectures and Compilation Techniques (PACT), September 2009.[PDF] [bib] [C4] M. Kinsy, M. H. Cho, T. Wen, G. E. Suh, M. Dijk, and S. Devadas: “Application-Aware Deadlock-Free Oblivious Routing.” In Proceedings of the International Symposium on Computer Architecture (ISCA), June 2009.[PDF] [bib] [C3] K. S. Shim, M. H. Cho, M. Kinsy, T. Wen, M. Lis , G. E. Suh, and S. Devadas: “A Comparison of Static and Dynamic Virtual Channel Allocation in Oblivious Routing.” In Proceedings of the International Symposium on Networks-on-Chip (NOCS), May 2009.[PDF] [bib] 2008 [C2] M. H. Cho, C-C. Cheng, M. Kinsy, G. E. Suh, and S. Devadas: “Diastolic Arrays: Throughput-Driven Reconfigurable Computing.” In Proceedings of the International Conference on Computer-Aided Design (ICCAD), November 2008.[PDF] [bib] 2007 [C1] M. Kinsy and Z. Lacroix: “Storing Efficiently Bioinformatics Workflows.” In Proceedings of the 2007 IEEE International Symposium on Bioinformatics Bioengineering (BIBE), October 2007.[PDF] [bib] PEER-REVIEWED WORKSHOPS [W7] M. A. Kinsy, D. Kava, A. Ehret and M. Mark: “Sphinx: A Secure Architecture Based on Binary Code Diversification and Execution Obfuscation”. Boston Area Architecture 2018 Workshop (BARC18), January 2018.[PDF] [bib] [W6] M. A. Kinsy, M. Isakov, A. Ehret and D. Kava: “SAPA: Self-Aware Polymorphic Architecture”, Boston Area Architecture 2018 Workshop (BARC18), January 2018.[PDF] [bib] [W5] M. Isakov and M. A. Kinsy: “ClosNets: a Priori Sparse Topologies for Faster DNN Training”, Boston Area Architecture 2018 Workshop (BARC18), January 2018.[PDF] [bib] 2017 [W4] M. Kinsy, R. Agrawal and H. Nguyen: “Fast Processing of Large Graph Applications Using Asynchronous Architecture.” Boston Area Architecture 2017 Workshop (BARC17), January 2017.[PDF] [bib] 2012 [W4] M. Kinsy and S. Devadas: “Heracles 2.0: A Tool for Design Space Exploration of Multi/Many-core Processors.” Workshop on the Intersections of Computer Architecture and Reconfigurable Logic (CARL 2012) Co-located with ISCA-39, June 2012.[PDF] [bib] 2009 [W3] M. H. Cho, M. Lis, K. S. Shim, M. Kinsy, and S. Devadas: “Path-Based, Randomized, Oblivious Routing.” In Proceedings of the 2nd International Workshop on Network-on-Chip Architectures (NoCArc’09), December 2009.[PDF] [bib] 2007 [W2] Q. Shao, M. Kinsy and Y. Chen: “Storing and Discovering Critical Workflows from Log in Scientific Exploration.” In Proceedings of the 2007 IEEE International Workshop on Scientific Workflows (SWF), July 2007.[PDF] [bib] [W1] M. Kinsy, Z. Lacroix, C. Legendre, P. Wlodarczyk, N. Yacoubi Ayadi: “ProtocolDB: Storing Scientific Protocols with a Domain Ontology.” Lecture Notes in Computer Science by Springer-Verlag. WISE Workshops 2007: 17-28[PDF] [bib] POSTERS 2017 [P4] R. S. Agrawal and M. A. Kinsy: “Adaptive-Approximate Cache Architecture.” In the 3rd Career Workshop for Women and Minorities in Computer Architecture, held in conjunction with the 50th IEEE/ACM International Symposium on Microarchitecture (MICRO-50), October 2017.[PDF] [bib] 2016 [P3] S. Khadka, S. Ergullu-Koehnen, B. Gravelle, and M. Kinsy: “Neural network based predictive routing for network-on-chip architectures.” Work-in-Progress Presentation at 53rd Design Automation Conference (DAC 2016), June 2016.[PDF] [bib] [P2] P. Ren, M. Kinsy, C. Yang, B. Gravelle, S. Khadka, and N. Zheng: “Copal: Connectivity preserving algorithm for network-on-chip power-gating.” Work-in-Progress Presentation at 53rd Design Automation Conference (DAC 2016), June 2016.[PDF] [bib] 2012 [P1] M. Kinsy, J. Poon, I. Celanovic, O. Khan, and S. Devadas: “A Multicore Architecture for Control and Emulation of Power Electronics and Smart Grid Systems Under Hard Real- Time Constraints.” Work-in-Progress Presentation at 49th Design Automation Conference (DAC 2012), June 2012.[PDF] [bib] REPORTS 2017 [R2] P. Ren, M. Kinsy, M. Zhu, S. Khadka, M. Isakov, A. Ramrakhyani, T. Krishna, and N. Zheng. “FASHION: Fault-Aware Self-Healing Intelligent On-chip Network.” arXiv preprint arXiv:1702.02313, 2017.[PDF] [bib] 2009 [R1] M. Kinsy and R. Uhler: “SHA-3: FPGA implementation of ESSENCE and ECHO hash algorithm candidates using Bluespec.” CSG-Report, CSAIL, MIT, May, 2009.[PDF] [bib] |