Yours truly.
hello!
I was a postdoctoral associate at the Massachusetts Institute of Technology mentored by Professor Daniel Sanchez. I received my PhD in Electrical Engineering and Computer Science from MIT in May 2022.
I focus on accelerating applications that haven't been adequately served by conventional computer architectures. In particular, my dissertation research has shown that irregular applications (those with data-dependent memory accesses, unpredictable branches) can be efficiently accelerated through fine-grain pipeline parallelism. There, I explored solutions from the core microarchitecture level to specialized spatial architectures.
In what time remains I develop a place-and-route tool for Minecraft circuits, maintain (and ride) vintage Schwinn bicycles, shoot film, and dance the Lindy Hop.
contact
To contact me, join my initials (qmn) and mit.edu with the @ sign.
recent news
- You can go for a drive. Caution: not useful.
- In 2021, 2022, and 2023, I helped run SIGTBD, MIT CSAIL's joke conference.
- In the summer of 2022, I bicycled across America 🚴 🇺🇸
- In May 2022, I defended my Ph.D. thesis and submitted my dissertation?!
- You can tell the time. Caution: not useful.
publications
Publications here are for academic or personal uses only. The journey of a thousand publications begins with a single workshop.
- Phloem: Automatic Acceleration of Irregular Applications with Fine-Grain Pipeline Parallelism, Quan M. Nguyen, Daniel Sanchez, Proceedings of the 29th International Symposium on High-Performance Computer Architecture (HPCA-29), Montreal, QC, February 2023. [pdf] [slides pdf]
- Accelerating Irregular Applications with Pipeline Parallelism, Quan M. Nguyen, Ph.D. Thesis, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA, May 2022. [pdf]
- Fifer: Practical Acceleration of Irregular Applications on Reconfigurable Architectures, Quan M. Nguyen, Daniel Sanchez, Proceedings of the 54th International Symposium on Microarchitecture (MICRO-54), Athens, Greece, October 2021. [pdf] [slides pdf]
- Pipette: Improving Core Utilization on Irregular Applications through Intra-Core Pipeline Parallelism, Quan M. Nguyen, Daniel Sanchez, Proceedings of the 53rd International Symposium on Microarchitecture (MICRO-53), Athens, Greece, October 2020. [pdf] [slides pdf]
- Towards Thousand-Core RISC-V Shared Memory Systems, Quan M. Nguyen, the 5th RISC-V Workshop, Mountain View, CA, November 2016. [youtube]
- Synchronization in Timestamp-Based Cache Coherence Protocols, Quan M. Nguyen, S.M. Thesis, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA, June 2016. [pdf]
- A Case for MVPs: Mixed-Precision Vector Processors, Albert Ou, Quan M. Nguyen, Yunsup Lee, Krste Asanović, 2nd International Workshop on Parallelism in Mobile Platforms (PRISM-2) at the 41st International Symposium on Computer Architecture (ISCA-41), Minneapolis, MN, June 2014. [pdf]