SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects
Jacob Postman, Tushar Krishna, Christopher Edmonds, Li-Shiuan Peh, and Patrick Chiang
A 64-bit, 8x8 mesh network-on-chip (NoC) is
presented that uses both new architectural and circuit design
techniques to improve on-chip network energy-efficiency, latency,
and throughput. First, we propose token flow control, which
enables bypassing of flit buffering in routers, thereby reducing
buffer size and their power consumption. We also incorporate reduced-swing signaling in on-chip links and crossbars
to minimize datapath interconnect energy. The 64-node NoC
is experimentally validated with a 2x2 test chip in 90 nm,
1.2 V CMOS that incorporates traffic generators to emulate the
traffic of the full network. Compared with a fully synthesized
baseline 8x8 NoC architecture designed to meet the same peak
throughput, the fabricated prototype reduces network latency by
20% under uniform random traffic, when both networks are run
at their maximum operating frequencies. When operated at the
same frequencies, the SWIFT NoC reduces network power by
38% and 25% at saturation and low loads, respectively.